Rafael Espindola 201a551929 Fix the interpretation of a 0 st_name. ... The ELF spec is very clear: ----------------------------------------------------------------------------- If the value is non-zero, it represents a string table index that gives the symbol name. Otherwise, the symbol table entry has no name. -------------------------------------------------------------------------- In particular, a st_name of 0 most certainly doesn't mean that the symbol has the same name as the section. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238899 91177308-0d34-0410-b5e6-96231b3b80d8		2015-06-03 05:14:22 +00:00
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AArch64	AArch64: fix typo in SMIN far atomics and add tests	2015-06-02 18:37:20 +00:00
ARM	Fix the interpretation of a 0 st_name.	2015-06-03 05:14:22 +00:00
AsmParser	Relax these tests a bit.	2015-05-22 21:37:13 +00:00
COFF	Revise test to run llc and llvm-mc separately.	2015-05-28 21:49:50 +00:00
Disassembler	AArch64: fix typo in SMIN far atomics and add tests	2015-06-02 18:37:20 +00:00
ELF	Fix the interpretation of a 0 st_name.	2015-06-03 05:14:22 +00:00
Hexagon	[Hexagon] Disassembling, printing, and emitting instructions a whole-bundle at a time which is the semantic unit for Hexagon. Fixing tests to use the new format. Disabling tests in the direct object emission path for a followup patch.	2015-05-29 14:44:13 +00:00
MachO	AArch64: work around ld64 bug more aggressively.	2015-05-18 22:07:20 +00:00
Markup
Mips	[mips] [IAS] Reformat mips-expansions.s. NFC.	2015-06-02 10:34:10 +00:00
PowerPC	Add support for VSX FMA single-precision instructions to the PPC back end	2015-05-29 17:13:25 +00:00
R600	R600/SI: Add assembler support for all CI and VI VOP2 instructions	2015-05-26 15:55:52 +00:00
Sparc	Sparc: support the "set" synthetic instruction.	2015-05-18 16:43:33 +00:00
SystemZ	[SystemZ] Add z13 vector facility and MC support	2015-05-05 19:23:40 +00:00
X86	AVX-512: Implemented VRANGESD and VRANGESS instructions for SKX Implemented DAG lowering for all these forms.	2015-06-02 14:12:54 +00:00