Commit Graph

4420 Commits

Author SHA1 Message Date
Rafael Espindola
201a551929 Fix the interpretation of a 0 st_name.
The ELF spec is very clear:

-----------------------------------------------------------------------------
If the value is non-zero, it represents a string table index that gives the
symbol name. Otherwise, the symbol table entry has no name.
--------------------------------------------------------------------------

In particular, a st_name of 0 most certainly doesn't mean that the symbol has
the same name as the section.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238899 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-03 05:14:22 +00:00
Tim Northover
33d75a269c AArch64: fix typo in SMIN far atomics and add tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238858 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-02 18:37:20 +00:00
Elena Demikhovsky
6628cb50bd AVX-512: Implemented VRANGESD and VRANGESS instructions for SKX Implemented DAG lowering for all these forms.
Added tests for encoding.

By Igor Breger (igor.breger@intel.com)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238834 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-02 14:12:54 +00:00
Vladimir Sukharev
1e7e9b1881 [AArch64] Add v8.1a atomic instructions
Patch by: Tom Coxon

Reviewers: t.p.northover

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8501


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238818 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-02 10:58:41 +00:00
Toma Tabacu
01cf1d3ef3 [mips] [IAS] Reformat mips-expansions.s. NFC.
Summary:
Make mips-expansions.s more readable by grouping the instructions with their respective CHECK's.
This test is going to get a lot bigger soon and it will become essentially unreadable if the current formatting is kept.

I've also made the comments more useful and accurate, and I've restricted the RUN lines to under 80 columns.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10089

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238817 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-02 10:34:10 +00:00
Daniel Sanders
fa82cb6244 [mips] Test both %dtprel_hi and %dtprel_lo instead of testing %dtprel_hi twice.
The second %dtprel_hi is used on an addiu so it looks like a copy/paste error.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238815 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-02 10:09:08 +00:00
Daniel Sanders
ad601b6b90 [mips] Expand tabs in test/MC/Mips/mips-relocations.s
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238814 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-02 10:02:00 +00:00
Toma Tabacu
a5f14070fa [mips] [IAS] Add support for the .set softfloat/hardfloat directives.
Summary: These directives are used to set the current value of the SoftFloat feature.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits, mpf

Differential Revision: http://reviews.llvm.org/D9074

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238813 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-02 09:48:04 +00:00
Elena Demikhovsky
d929045eb5 AVX-512: Implemented VFIXUPIMMSD and VFIXUPIMMSS instructions for KNL
Implemented DAG lowering for all these forms.
Added tests for encoding.

By Igor Breger (igor.breger@intel.com)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238811 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-02 08:28:57 +00:00
Asaf Badouh
aa9e1c528b revert 238809
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238810 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-02 07:45:19 +00:00
Asaf Badouh
82fa06895e AVX-512: Implemented GETEXP instruction for KNL and SKX
Added rounding mode modifier for SQRTPS/PD
Added tests for encoding and intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238809 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-02 07:18:14 +00:00
Rafael Espindola
872808e946 Fix relocation selection for foo-. on mips.
This handles only the 32 bit case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238751 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-01 15:10:51 +00:00
Asaf Badouh
b06d15c70f First commit test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238745 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-01 13:56:00 +00:00
Elena Demikhovsky
af0e519127 AVX-512: Implemented VRANGEPD and VRANGEPD instructions for SKX.
Implemented DAG lowering for all these forms.
Added tests for encoding.

By Igor Breger (igor.breger@intel.com)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238738 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-01 11:05:34 +00:00
Elena Demikhovsky
8e12b59b13 AVX-512: added all forms of VPSHUFD and VPSHUFHW, VPSHUFLW
including encodings.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238729 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-01 07:17:23 +00:00
Elena Demikhovsky
9029910d9f AVX-512: Implemented VFIXUPIMMPD and VFIXUPIMMPS instructions for KNL and SKX
Implemented DAG lowering for all these forms.
Added tests for encoding.

by Igor Breger (igor.breger@intel.com)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238728 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-01 06:50:49 +00:00
Nemanja Ivanovic
8493722975 Add support for VSX FMA single-precision instructions to the PPC back end
This patch corresponds to review:
http://reviews.llvm.org/D9941

It adds the various FMA instructions introduced in the version 2.07 of
the ISA along with the testing for them. These are operations on single
precision scalar values in VSX registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238578 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-29 17:13:25 +00:00
Colin LeMahieu
0ace3c01f7 [Hexagon] Disassembling, printing, and emitting instructions a whole-bundle at a time which is the semantic unit for Hexagon. Fixing tests to use the new format. Disabling tests in the direct object emission path for a followup patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238556 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-29 14:44:13 +00:00
Ahmed Bougacha
d4b59dcdba [TableGen][AsmMatcherEmitter] Only parse isolated tokens as registers.
Fixes PR23455, where, when TableGen generates the matcher from the
AsmString, it splits "cmp${cc}ss" into tokens, and the "ss" suffix
is recognized as the SS register.

I can't think of a situation where that's a feature, not a bug, hence:
when a token is "isolated", i.e., it is followed and preceded by
separators, it shouldn't be parsed as a register.

Differential Revision: http://reviews.llvm.org/D9844


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238536 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-29 01:03:37 +00:00
Rafael Espindola
fb48de619e Don't special case undefined symbol when deciding the symbol order.
ELF has no restrictions on where undefined symbols go relative to other defined
symbols. In fact, gas just sorts them together. Do the same.

This was there since r111174 probably just because the MachO writer has it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238513 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-28 21:59:34 +00:00
Andy Ayers
588f5f0cbb Revise test to run llc and llvm-mc separately.
Differential Revision: http://reviews.llvm.org/D10066

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238508 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-28 21:49:50 +00:00
Kai Nacke
95fa1db8f5 [mips] Add new format for dmtc2/dmfc2 for Octeon CPUs.
Octeon CPUs use dmtc2 rt,imm16 and dmfcp2 rt,imm16 for the crypto coprocessor.
E.g. dmtc2 rt,0x4057 starts calculation of sha-1.

I had to introduce a new deconding namespace to avoid a decoding conflict.

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D10083


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238439 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-28 16:23:16 +00:00
Rafael Espindola
c4e38f605e Don't create an unused _GLOBAL_OFFSET_TABLE_.
This was a bug for bug compatibility with gas that is completely unnecessary.
If a _GLOBAL_OFFSET_TABLE_ symbol is used, it will already be created by
the time we get to the ELF writer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238432 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-28 15:20:00 +00:00
Renato Golin
a052a77187 ARMTargetParser: Normalising build attributes
Now that most of the methods in Clang and LLVM that were parsing arch/cpu/fpu
strings are using ARMTargetParser, it's time to make it a bit more conforming
with what the ABI says.

This commit adds some clarification on what build attributes are accepted and
which are "non-standard". It also makes clear that the "defaultCPU" and
"defaultArch" methods were really just build attribute getters.

It also diverges from GCC's behaviour to say that armv2/armv3 are really an
ARMv4 in the build attributes, when the ABI has a clear state for that: Pre-v4.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238344 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-27 18:15:37 +00:00
Zoran Jovanovic
dbab00a2d4 [mips][microMIPSr6] Implement SEB and SEH instructions
Differential Revision: http://reviews.llvm.org/D9739


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238333 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-27 15:39:47 +00:00
Jozef Kolek
b8124ac882 [mips][microMIPSr6] Implement BEQZALC, BGEZALC, BGTZALC, BLEZALC, BLTZALC and BNEZALC instructions
This patch implements microMIPS32r6 BEQZALC, BGEZALC, BGTZALC, BLEZALC, BLTZALC
and BNEZALC instructions using mapping.

Differential Revision: http://reviews.llvm.org/D10031


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238325 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-27 14:19:22 +00:00
Elena Demikhovsky
078088b790 AVX-512: Implemented all forms of sign-extend and zero-extend instructions for KNL and SKX
Implemented DAG lowering for all these forms.
Added tests for DAG lowering and encoding.

By Igor Breger (igor.breger@intel.com)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238301 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-27 08:15:19 +00:00
Tom Stellard
8352b74577 R600/SI: Add assembler support for all CI and VI VOP2 instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238211 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-26 15:55:52 +00:00
Kit Barton
948ecae20e This patch adds support for the vector quadword add/sub instructions introduced
in POWER8:

vadduqm
vaddeuqm
vaddcuq
vaddecuq
vsubuqm
vsubeuqm
vsubcuq
vsubecuq
In addition to adding the instructions themselves, it also adds support for the
v1i128 type for intrinsics (Intrinsics.td, Function.cpp, and
IntrinsicEmitter.cpp).

http://reviews.llvm.org/D9081


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238144 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-25 15:49:26 +00:00
Benjamin Kramer
083d79a583 [AArch64] Clean up the ELF streamer a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238102 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-23 16:39:10 +00:00
Rafael Espindola
7c4f3dcc5e Produce a single string table in a ELF .o
Normally an ELF .o has two string tables, one for symbols, one for section
names.

With the scheme of naming sections like ".text.foo" where foo is a symbol,
there is a big potential saving in using a single one.

Building llvm+clang+lld with master and with this patch the results were:

master:                          193,267,008 bytes
patch:                           186,107,952 bytes
master non unique section names: 183,260,192 bytes
patch non unique section names:  183,118,632 bytes

So using non usique saves 10,006,816 bytes, and the patch saves 7,159,056 while
still using distinct names for the sections.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238073 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-22 23:58:30 +00:00
Rafael Espindola
6af60ebd57 Relax these tests a bit.
It is not relevant where in the string table the name is located.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238053 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-22 21:37:13 +00:00
Bill Schmidt
490d207be4 [PPC64] Add support for clrbhrb, mfbhrbe, rfebb.
This patch adds support for the ISA 2.07 additions involving the
branch history rolling buffer and event-based branching.  These will
not be used by typical applications, so built-in support is not
required.  They will only be available via inline assembly.

Assembly/disassembly tests are included in the patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238032 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-22 16:44:10 +00:00
John Brawn
8a95a5095d [ARM] Fix typo in subtarget feature list for 7em triple
The list of subtarget features for the 7em triple contains 't2xtpk',
which actually disables that subtarget feature. Correct that to
'+t2xtpk' and test that the instructions enabled by that feature do
actually work.

Differential Revision: http://reviews.llvm.org/D9936


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238022 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-22 14:16:22 +00:00
Nemanja Ivanovic
24ed4de261 Add support for VSX scalar single-precision arithmetic in the PPC target
http://reviews.llvm.org/D9891
Following up on the VSX single precision loads and stores added earlier, this
adds support for elementary arithmetic operations on single precision values
in VSX registers. These instructions utilize the new VSSRC register class.
Instructions added:
xsaddsp
xsdivsp
xsmulsp
xsresp
xsrsqrtesp
xssqrtsp
xssubsp


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237937 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-21 19:32:49 +00:00
Toma Tabacu
cebe8f8b05 [mips] [IAS] Add 2 missing CHECK directives for fixups in mips-expansions.s.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237884 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-21 10:04:39 +00:00
Zoran Jovanovic
70d1005bbd [mips][microMIPSr6] Implement NOR, OR, ORI, XOR and XORI instructions
Differential Revision: http://reviews.llvm.org/D8800


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237697 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-19 14:12:55 +00:00
Zoran Jovanovic
94ddfe5e09 [mips][microMIPSr6] Implement AND and ANDI instructions
Differential Revision: http://reviews.llvm.org/D8772


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237696 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-19 13:32:31 +00:00
Zoran Jovanovic
7004ac8b5a [mips][microMIPSr6] Implement DIV, DIVU, MOD and MODU instructions
Differential Revision: http://reviews.llvm.org/D8769


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237685 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-19 11:21:37 +00:00
Jozef Kolek
1193b61df0 [mips][microMIPSr6] Implement LSA instruction
This patch implements LSA instruction using mapping.

Differential Revision: http://reviews.llvm.org/D8919


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237634 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-18 23:12:10 +00:00
Tim Northover
6b57892624 AArch64: work around ld64 bug more aggressively.
ld64 currently mishandles internal pointer relocations (i.e.
ARM64_RELOC_UNSIGNED referred to by section & offset rather than symbol). The
existing __cfstring clause was an early discovery and workaround for this, but
the problem is wider and we should avoid such relocations wherever possible for
now.

This code should be reverted to allowing internal relocations as soon as
possible.

PR23437.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237621 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-18 22:07:20 +00:00
James Y Knight
ccafe05df1 Sparc: support the "set" synthetic instruction.
This pseudo-instruction expands into 'sethi' and 'or' instructions,
or, just one of them, if the other isn't necessary for a given value.

Differential Revision: http://reviews.llvm.org/D9089

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237585 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-18 16:43:33 +00:00
James Y Knight
1467a41471 Sparc: Support PSR, TBR, WIM read/write instructions.
Differential Revision: http://reviews.llvm.org/D8971

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237582 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-18 16:38:47 +00:00
James Y Knight
ee058202fa Sparc: Add the "alternate address space" load/store instructions.
- Adds support for the asm syntax, which has an immediate integer
  "ASI" (address space identifier) appearing after an address, before
  a comma.

- Adds the various-width load, store, and swap in alternate address
  space instructions. (ldsba, ldsha, lduba, lduha, lda, stba, stha,
  sta, swapa)

This does not attempt to hook these instructions up to pointer address
spaces in LLVM, although that would probably be a reasonable thing to
do in the future.

Differential Revision: http://reviews.llvm.org/D8904

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237581 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-18 16:35:04 +00:00
James Y Knight
f272788a95 Add support for the Sparc implementation-defined "ASR" registers.
(Note that register "Y" is essentially just ASR0).

Also added some test cases for divide and multiply, which had none before.

Differential Revision: http://reviews.llvm.org/D8670

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237580 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-18 16:29:48 +00:00
Jozef Kolek
865eb964f3 [mips][microMIPSr6] Implement ALIGN and AUI instructions
This patch implements ALIGN and AUI instructions using mapping.

Differential Revision: http://reviews.llvm.org/D8782


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237563 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-18 11:44:30 +00:00
Elena Demikhovsky
c4a426be4f AVX-512: Added VBROADCASTF64X4, VBROADCASTF64X2, VBROADCASTI32X8, and other instructions from this set
Added encoding tests.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237557 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-18 06:42:57 +00:00
Bill Schmidt
24f0469865 [PPC64] Add vector pack/unpack support from ISA 2.07
This patch adds support for the following new instructions in the
Power ISA 2.07:

  vpksdss
  vpksdus
  vpkudus
  vpkudum
  vupkhsw
  vupklsw

These instructions are available through the vec_packs, vec_packsu,
vec_unpackh, and vec_unpackl built-in interfaces.  These are
lane-sensitive instructions, so the built-ins have different
implementations for big- and little-endian, and the instructions must
be marked as killing the vector swap optimization for now.

The first three instructions perform saturating pack operations.  The
fourth performs a modulo pack operation, which means it can be
represented with a vector shuffle, and conversely the appropriate
vector shuffles may cause this instruction to be generated.  The other
instructions are only generated via built-in support for now.

Appropriate tests have been added.

There is a companion patch to clang for the rest of this support.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237499 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-16 01:02:12 +00:00
Toma Tabacu
039eb5a7b8 [mips] [IAS] Fix expansion of negative 32-bit immediates for LI/DLI.
Summary:
To maintain compatibility with GAS, we need to stop treating negative 32-bit immediates as 64-bit values when expanding LI/DLI.
This currently happens because of sign extension.

To do this we need to choose the 32-bit value expansion for values which use their upper 33 bits only for sign extension (i.e. no 0's, only 1's).

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8662

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237428 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-15 09:42:11 +00:00
Toma Tabacu
e6f281a2ff [mips] [IAS] Enforce .set nomacro.
Summary: When used, ".set nomacro" causes warning messages to be reported when we expand pseudo-instructions to multiple machine instructions.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9564

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237366 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-14 14:51:32 +00:00