Colin LeMahieu 6fc90b32e3 [Hexagon] Adding a number of other tests for min/max instructions and loading i1s. ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239935 91177308-0d34-0410-b5e6-96231b3b80d8

2015-06-17 20:29:33 +00:00

..

intrinsics

[Hexagon] Making intrinsic tests agnostic to register allocation. Narrowing intrinsic parameters to appropriate width.

2015-06-12 19:57:32 +00:00

vect

[Hexagon] Add support for vector instructions

2015-03-19 16:33:08 +00:00

absaddr-store.ll

[Hexagon] Adding some codegen tests and updating some to match spec.

2015-06-13 21:46:39 +00:00

absimm.ll

[Hexagon] Adding some codegen tests and updating some to match spec.

2015-06-13 21:46:39 +00:00

adde.ll

[Hexagon] Some cleanup of instruction selection code

2015-04-22 21:17:00 +00:00

addh-sext-trunc.ll

[Hexagon] Adding some codegen tests and updating some to match spec.

2015-06-13 21:46:39 +00:00

addh-shifted.ll

[Hexagon] Adding some codegen tests and updating some to match spec.

2015-06-13 21:46:39 +00:00

addh.ll

[Hexagon] Adding some codegen tests and updating some to match spec.

2015-06-13 21:46:39 +00:00

addrmode-indoff.ll

[Hexagon] Adding some codegen tests and updating some to match spec.

2015-06-13 21:46:39 +00:00

alu64.ll

[Hexagon] Update AnalyzeBranch, etc target hooks

2015-05-08 16:16:29 +00:00

always-ext.ll

[Hexagon] Adding some codegen tests and updating some to match spec.

2015-06-13 21:46:39 +00:00

args.ll

[Hexagon] Adding some codegen tests and updating some to match spec.

2015-06-13 21:46:39 +00:00

ashift-left-right.ll

[Hexagon] Adding some codegen tests and updating some to match spec.

2015-06-13 21:46:39 +00:00

barrier-flag.ll

[Hexagon] Adding some codegen tests and updating some to match spec.

2015-06-13 21:46:39 +00:00

base-offset-addr.ll

[Hexagon] Adding some codegen tests and updating some to match spec.

2015-06-13 21:46:39 +00:00

base-offset-post.ll

[Hexagon] Adding some codegen tests and updating some to match spec.

2015-06-13 21:46:39 +00:00

block-addr.ll

[Hexagon] Use A2_tfrsi for constant pool and jump table addresses

2015-04-22 18:25:53 +00:00

BranchPredict.ll

[Hexagon] Some cleanup of instruction selection code

2015-04-22 21:17:00 +00:00

brev_ld.ll

[Hexagon] Intrinsics for circular and bit-reversed loads and stores

2015-03-18 16:23:44 +00:00

brev_st.ll

[Hexagon] Intrinsics for circular and bit-reversed loads and stores

2015-03-18 16:23:44 +00:00

calling-conv-2.ll

[PATCH] [HEXAGON] Add a test program to verify calling convention

2015-05-12 20:13:10 +00:00

cext-check.ll

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cext-valid-packet1.ll

[Hexagon] Disassembling, printing, and emitting instructions a whole-bundle at a time which is the semantic unit for Hexagon. Fixing tests to use the new format. Disabling tests in the direct object emission path for a followup patch.

2015-05-29 14:44:13 +00:00

cext-valid-packet2.ll

[Hexagon] Disassembling, printing, and emitting instructions a whole-bundle at a time which is the semantic unit for Hexagon. Fixing tests to use the new format. Disabling tests in the direct object emission path for a followup patch.

2015-05-29 14:44:13 +00:00

cext.ll

[Hexagon] Adding a number of other tests for min/max instructions and loading i1s.

2015-06-17 20:29:33 +00:00

cexti16.ll

[Hexagon] Adding a number of other tests for min/max instructions and loading i1s.

2015-06-17 20:29:33 +00:00

circ_ld.ll

[Hexagon] Intrinsics for circular and bit-reversed loads and stores

2015-03-18 16:23:44 +00:00

circ_ldd_bug.ll

[Hexagon] Intrinsics for circular and bit-reversed loads and stores

2015-03-18 16:23:44 +00:00

circ_ldw.ll

[Hexagon] Intrinsics for circular and bit-reversed loads and stores

2015-03-18 16:23:44 +00:00

circ_st.ll

[Hexagon] Intrinsics for circular and bit-reversed loads and stores

2015-03-18 16:23:44 +00:00

clr_set_toggle.ll

Missed testcase for r232577

2015-03-18 00:44:46 +00:00

cmp_pred2.ll

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cmp_pred_reg.ll

[Hexagon] Adding some compare tests, fixing existing XFAILed tests, and removing mcpu=hexagonv4 since that's the minimum version anyway.

2015-06-17 17:19:05 +00:00

cmp_pred.ll

[Hexagon] Adding some compare tests, fixing existing XFAILed tests, and removing mcpu=hexagonv4 since that's the minimum version anyway.

2015-06-17 17:19:05 +00:00

cmp-extend.ll

[Hexagon] Adding some compare tests, fixing existing XFAILed tests, and removing mcpu=hexagonv4 since that's the minimum version anyway.

2015-06-17 17:19:05 +00:00

cmp-promote.ll

[Hexagon] Adding some compare tests, fixing existing XFAILed tests, and removing mcpu=hexagonv4 since that's the minimum version anyway.

2015-06-17 17:19:05 +00:00

cmp-to-genreg.ll

[Hexagon] Adding some compare tests, fixing existing XFAILed tests, and removing mcpu=hexagonv4 since that's the minimum version anyway.

2015-06-17 17:19:05 +00:00

cmp-to-predreg.ll

[Hexagon] Adding some compare tests, fixing existing XFAILed tests, and removing mcpu=hexagonv4 since that's the minimum version anyway.

2015-06-17 17:19:05 +00:00

cmp.ll

[Hexagon] Adding some compare tests, fixing existing XFAILed tests, and removing mcpu=hexagonv4 since that's the minimum version anyway.

2015-06-17 17:19:05 +00:00

cmpb_pred.ll

[Hexagon] Adding some compare tests, fixing existing XFAILed tests, and removing mcpu=hexagonv4 since that's the minimum version anyway.

2015-06-17 17:19:05 +00:00

cmpb-eq.ll

[Hexagon] Adding some compare tests, fixing existing XFAILed tests, and removing mcpu=hexagonv4 since that's the minimum version anyway.

2015-06-17 17:19:05 +00:00

combine_ir.ll

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combine.ll

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compound.ll

[Hexagon] Adding functionality for searching for compound instruction pairs. Compound instructions reduce slot resource requirements freeing those packet slots up for more instructions.

2015-06-08 16:34:47 +00:00

convertdptoint.ll

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convertdptoll.ll

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convertsptoint.ll

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convertsptoll.ll

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ctlz-cttz-ctpop.ll

[Hexagon] Some cleanup of instruction selection code

2015-04-22 21:17:00 +00:00

ctor.ll

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dadd.ll

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dmul.ll

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double.ll

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doubleconvert-ieee-rnd-near.ll

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dsub.ll

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dualstore.ll

[Hexagon] Reapply r239097 with tests corrected for shuffling and duplexing.

2015-06-05 16:00:11 +00:00

duplex.ll

[Hexagon] Reapply r239097 with tests corrected for shuffling and duplexing.

2015-06-05 16:00:11 +00:00

expand-condsets-basic.ll

Expand MUX instructions early on Hexagon

2015-03-31 13:35:12 +00:00

expand-condsets-rm-segment.ll

Expand MUX instructions early on Hexagon

2015-03-31 13:35:12 +00:00

expand-condsets-undef.ll

Expand MUX instructions early on Hexagon

2015-03-31 13:35:12 +00:00

extload-combine.ll

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fadd.ll

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fcmp.ll

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float.ll

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floatconvert-ieee-rnd-near.ll

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fmul.ll

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frame.ll

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fsub.ll

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fusedandshift.ll

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gp-plus-offset-load.ll

[opaque pointer type] Add textual IR support for explicit type parameter to gep operator

2015-03-13 18:20:45 +00:00

gp-plus-offset-store.ll

[opaque pointer type] Add textual IR support for explicit type parameter to gep operator

2015-03-13 18:20:45 +00:00

gp-rel.ll

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hwloop1.ll

[Hexagon] Generate more hardware loops

2015-05-08 20:18:21 +00:00

hwloop2.ll

[Hexagon] Generate more hardware loops

2015-05-08 20:18:21 +00:00

hwloop3.ll

[Hexagon] Generate more hardware loops

2015-05-08 20:18:21 +00:00

hwloop4.ll

[Hexagon] Generate more hardware loops

2015-05-08 20:18:21 +00:00

hwloop5.ll

[Hexagon] Generate hardware loop for a vectorized loop

2015-05-14 20:36:19 +00:00

hwloop-cleanup.ll

[Hexagon] Handle ENDLOOP0 in InsertBranch and RemoveBranch

2015-03-18 15:56:43 +00:00

hwloop-const.ll

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hwloop-crit-edge.ll

[Hexagon] Generate hardware loop when loop has a critical edge

2015-05-13 14:54:24 +00:00

hwloop-dbg.ll

IR: Give 'DI' prefix to debug info metadata

2015-04-29 16:38:44 +00:00

hwloop-le.ll

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hwloop-loop1.ll

[Hexagon] Generate loop1 instruction for nested loops

2015-05-13 17:56:03 +00:00

hwloop-lt1.ll

[Hexagon] Adding a number of other tests for min/max instructions and loading i1s.

2015-06-17 20:29:33 +00:00

hwloop-lt.ll

[Hexagon] Adding a number of other tests for min/max instructions and loading i1s.

2015-06-17 20:29:33 +00:00

hwloop-missed.ll

[Hexagon] Generate more hardware loops

2015-05-08 20:18:21 +00:00

hwloop-ne.ll

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hwloop-ph-deadcode.ll

[Hexagon] Remove dead constant assignment in hardware loop pass

2015-05-14 17:31:40 +00:00

hwloop-pos-ivbump1.ll

[Hexagon] Check for underflow/wrap in hardware loop pass

2015-05-14 14:15:08 +00:00

hwloop-preheader.ll

[Hexagon] Generate more hardware loops

2015-05-08 20:18:21 +00:00

hwloop-range.ll

[Hexagon] Use constant extenders to fix up hardware loops

2015-04-27 14:16:43 +00:00

hwloop-recursion.ll

[Hexagon] Check for underflow/wrap in hardware loop pass

2015-05-14 14:15:08 +00:00

hwloop-wrap2.ll

[Hexagon] Check for underflow/wrap in hardware loop pass

2015-05-14 14:15:08 +00:00

hwloop-wrap.ll

[Hexagon] Check for underflow/wrap in hardware loop pass

2015-05-14 14:15:08 +00:00

i1_VarArg.ll

[opaque pointer type] Add textual IR support for explicit type parameter to the call instruction

2015-04-16 23:24:18 +00:00

i8_VarArg.ll

[opaque pointer type] Add textual IR support for explicit type parameter to the call instruction

2015-04-16 23:24:18 +00:00

i16_VarArg.ll

[opaque pointer type] Add textual IR support for explicit type parameter to the call instruction

2015-04-16 23:24:18 +00:00

idxload-with-zero-offset.ll

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indirect-br.ll

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lit.local.cfg

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loadi1-G0.ll

[Hexagon] Adding a number of other tests for min/max instructions and loading i1s.

2015-06-17 20:29:33 +00:00

loadi1-v4-G0.ll

[Hexagon] Adding a number of other tests for min/max instructions and loading i1s.

2015-06-17 20:29:33 +00:00

loadi1-v4.ll

[Hexagon] Adding a number of other tests for min/max instructions and loading i1s.

2015-06-17 20:29:33 +00:00

loadi1.ll

[Hexagon] Adding a number of other tests for min/max instructions and loading i1s.

2015-06-17 20:29:33 +00:00

macint.ll

[Hexagon] Some cleanup of instruction selection code

2015-04-22 21:17:00 +00:00

maxd.ll

[Hexagon] Adding a number of other tests for min/max instructions and loading i1s.

2015-06-17 20:29:33 +00:00

maxh.ll

[Hexagon] Adding a number of other tests for min/max instructions and loading i1s.

2015-06-17 20:29:33 +00:00

maxud.ll

[Hexagon] Adding a number of other tests for min/max instructions and loading i1s.

2015-06-17 20:29:33 +00:00

maxuw.ll

[Hexagon] Adding a number of other tests for min/max instructions and loading i1s.

2015-06-17 20:29:33 +00:00

maxw.ll

[Hexagon] Adding a number of other tests for min/max instructions and loading i1s.

2015-06-17 20:29:33 +00:00

mem-fi-add.ll

[Hexagon] Patterns for frame index with offset for isel

2015-04-21 21:28:03 +00:00

memops1.ll

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memops2.ll

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memops3.ll

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memops.ll

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mind.ll

[Hexagon] Adding a number of other tests for min/max instructions and loading i1s.

2015-06-17 20:29:33 +00:00

minu-zext-8.ll

[Hexagon] Adding a number of other tests for min/max instructions and loading i1s.

2015-06-17 20:29:33 +00:00

minu-zext-16.ll

[Hexagon] Adding a number of other tests for min/max instructions and loading i1s.

2015-06-17 20:29:33 +00:00

minud.ll

[Hexagon] Adding a number of other tests for min/max instructions and loading i1s.

2015-06-17 20:29:33 +00:00

minuw.ll

[Hexagon] Adding a number of other tests for min/max instructions and loading i1s.

2015-06-17 20:29:33 +00:00

minw.ll

[Hexagon] Adding a number of other tests for min/max instructions and loading i1s.

2015-06-17 20:29:33 +00:00

misaligned-access.ll

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mpy.ll

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newvaluejump2.ll

[Hexagon] Some cleanup of instruction selection code

2015-04-22 21:17:00 +00:00

newvaluejump.ll

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newvaluestore.ll

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opt-fabs.ll

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opt-fneg.ll

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packetize_cond_inst.ll

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postinc-load.ll

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postinc-store.ll

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pred-absolute-store.ll

[Hexagon] Removing unused patterns.

2015-03-09 23:08:46 +00:00

pred-gp.ll

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pred-instrs.ll

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predicate-copy.ll

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relax.ll

[Hexagon] Reapply 238772 OSABI was not correctly set, added empty_elf test to make sure it is.

2015-06-03 17:34:16 +00:00

remove_lsr.ll

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remove-endloop.ll

[Hexagon] Update AnalyzeBranch, etc target hooks

2015-05-08 16:16:29 +00:00

shrink-frame-basic.ll

[Hexagon] Shrink-wrap stack frame (Hexagon-specific)

2015-04-23 16:05:39 +00:00

signed_immediates.ll

[Hexagon] Adding decoders for signed operands and ensuring all signed operand types disassemble correctly.

2015-06-10 16:52:32 +00:00

simple_addend.ll

[Hexagon] Adding MC ELF streamer and updating addend relocation test which shows correct ELF symbol.

2015-06-17 03:06:16 +00:00

simpletailcall.ll

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split-const32-const64.ll

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stack-align1.ll

[Hexagon] Add testcases for stack alignment and variable-sized objects

2015-04-23 15:12:49 +00:00

stack-align2.ll

[Hexagon] Add testcases for stack alignment and variable-sized objects

2015-04-23 15:12:49 +00:00

stack-alloca1.ll

[Hexagon] Add testcases for stack alignment and variable-sized objects

2015-04-23 15:12:49 +00:00

stack-alloca2.ll

[Hexagon] Add testcases for stack alignment and variable-sized objects

2015-04-23 15:12:49 +00:00

static.ll

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struct_args_large.ll

[Hexagon] Reapply r231699. Remove assumption that second operand is an immediate when checking if A2_tfrsi is combinable.

2015-03-09 21:48:13 +00:00

struct_args.ll

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sube.ll

[Hexagon] Reapply r239097 with tests corrected for shuffling and duplexing.

2015-06-05 16:00:11 +00:00

tail-call-mem-intrinsics.ll

Allow memory intrinsics to be tail calls

2015-04-13 17:16:45 +00:00

tail-call-trunc.ll

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tfr-to-combine.ll

[Hexagon] Use A2_tfrsi for constant pool and jump table addresses

2015-04-22 18:25:53 +00:00

union-1.ll

Remove unused complex patterns for addressing modes on Hexagon.

2015-03-12 16:44:50 +00:00

vaddh.ll

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validate-offset.ll

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zextloadi1.ll

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