llvm-6502/test/CodeGen
2013-10-09 23:36:17 +00:00
..
AArch64 AArch64: enable MISched by default. 2013-10-09 07:53:57 +00:00
ARM Struct byval: use the correct alignment for loads generated to load 2013-10-07 19:47:53 +00:00
CPP
Generic Change objectsize intrinsic to accept different address spaces. 2013-10-07 18:06:48 +00:00
Hexagon
Inputs
Mips [mips] Do not generate INS/EXT nodes if target does not have support for 2013-10-09 23:36:17 +00:00
MSP430
NVPTX
PowerPC
R600 Add some xfaild R600 tests. 2013-10-08 18:06:36 +00:00
SPARC [Sparc] Disable tail call optimization for sparc64. 2013-10-09 12:50:39 +00:00
SystemZ [SystemZ] Add comparisons of high words and memory 2013-10-01 15:00:44 +00:00
Thumb
Thumb2
X86 AVX-512: Added VRCP28 and VRSQRT28 instructions and intrinsics. 2013-10-09 08:16:14 +00:00
XCore