Andrew Trick 2661b411cc I'm introducing a new machine model to simultaneously allow simple ... subtarget CPU descriptions and support new features of MachineScheduler. MachineModel has three categories of data: 1) Basic properties for coarse grained instruction cost model. 2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD). 3) Instruction itineraties for detailed per-cycle reservation tables. These will all live side-by-side. Any subtarget can use any combination of them. Instruction itineraries will not change in the near term. In the long run, I expect them to only be relevant for in-order VLIW machines that have complex contraints and require a precise scheduling/bundling model. Once itineraries are only actively used by VLIW-ish targets, they could be replaced by something more appropriate for those targets. This tablegen backend rewrite sets things up for introducing MachineModel type #2: per opcode/operand cost model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159891 91177308-0d34-0410-b5e6-96231b3b80d8		2012-07-07 04:00:00 +00:00
..
AsmMatcherEmitter.cpp	TableGen: AsmMatcher diagnostics preference detail.	2012-06-26 22:58:01 +00:00
AsmWriterEmitter.cpp	Write llvm-tblgen backends as functions instead of sub-classes.	2012-06-11 15:37:55 +00:00
AsmWriterInst.cpp
AsmWriterInst.h
CallingConvEmitter.cpp	Write llvm-tblgen backends as functions instead of sub-classes.	2012-06-11 15:37:55 +00:00
CMakeLists.txt	I'm introducing a new machine model to simultaneously allow simple	2012-07-07 04:00:00 +00:00
CodeEmitterGen.cpp	Write llvm-tblgen backends as functions instead of sub-classes.	2012-06-11 15:37:55 +00:00
CodeGenDAGPatterns.cpp
CodeGenDAGPatterns.h
CodeGenInstruction.cpp	Teach the AsmMatcherEmitter to allow InstAlias' where the suboperands of a complex operand are called out explicitly in the asm string.	2012-06-08 00:25:03 +00:00
CodeGenInstruction.h	Teach the AsmMatcherEmitter to allow InstAlias' where the suboperands of a complex operand are called out explicitly in the asm string.	2012-06-08 00:25:03 +00:00
CodeGenIntrinsics.h	rdar://11542750 - llvm.trap should be marked no return.	2012-05-27 23:20:41 +00:00
CodeGenRegisters.cpp	Fix typos found by http://github.com/lyda/misspell-check	2012-06-02 10:20:22 +00:00
CodeGenRegisters.h	Remove little semicolon that caused a lot of warnings.	2012-05-30 09:13:49 +00:00
CodeGenSchedule.cpp	I'm introducing a new machine model to simultaneously allow simple	2012-07-07 04:00:00 +00:00
CodeGenSchedule.h	I'm introducing a new machine model to simultaneously allow simple	2012-07-07 04:00:00 +00:00
CodeGenTarget.cpp	I'm introducing a new machine model to simultaneously allow simple	2012-07-07 04:00:00 +00:00
CodeGenTarget.h	I'm introducing a new machine model to simultaneously allow simple	2012-07-07 04:00:00 +00:00
DAGISelEmitter.cpp	Write llvm-tblgen backends as functions instead of sub-classes.	2012-06-11 15:37:55 +00:00
DAGISelMatcher.cpp
DAGISelMatcher.h
DAGISelMatcherEmitter.cpp
DAGISelMatcherGen.cpp	Teach TableGen to put chains on more instructions	2012-06-26 18:46:28 +00:00
DAGISelMatcherOpt.cpp
DFAPacketizerEmitter.cpp	Fix Windows build after r159281: s/iterator/const_iterator	2012-06-28 07:47:50 +00:00
DisassemblerEmitter.cpp	Write llvm-tblgen backends as functions instead of sub-classes.	2012-06-11 15:37:55 +00:00
EDEmitter.cpp	X86: add GATHER intrinsics (AVX2) in LLVM	2012-06-26 19:47:59 +00:00
FastISelEmitter.cpp	Write llvm-tblgen backends as functions instead of sub-classes.	2012-06-11 15:37:55 +00:00
FixedLenDecoderEmitter.cpp	Write llvm-tblgen backends as functions instead of sub-classes.	2012-06-11 15:37:55 +00:00
InstrInfoEmitter.cpp	I'm introducing a new machine model to simultaneously allow simple	2012-07-07 04:00:00 +00:00
IntrinsicEmitter.cpp	Write llvm-tblgen backends as functions instead of sub-classes.	2012-06-11 15:37:55 +00:00
LLVMBuild.txt	LLVMBuild: Remove trailing newline, which irked me.	2011-12-12 19:48:00 +00:00
Makefile
PseudoLoweringEmitter.cpp	Write llvm-tblgen backends as functions instead of sub-classes.	2012-06-11 15:37:55 +00:00
RegisterInfoEmitter.cpp	Write llvm-tblgen backends as functions instead of sub-classes.	2012-06-11 15:37:55 +00:00
SequenceToOffsetTable.h	enhance the intrinsic info stuff to emit encodings that don't fit in 32-bits into a	2012-05-17 15:55:41 +00:00
SetTheory.cpp	Teach tblgen's set theory "sequence" operator to support an optional stride operand.	2012-05-24 21:37:08 +00:00
SetTheory.h
StringToOffsetTable.h
SubtargetEmitter.cpp	I'm introducing a new machine model to simultaneously allow simple	2012-07-07 04:00:00 +00:00
TableGen.cpp	Write llvm-tblgen backends as functions instead of sub-classes.	2012-06-11 15:37:55 +00:00
TableGenBackends.h	Write llvm-tblgen backends as functions instead of sub-classes.	2012-06-11 15:37:55 +00:00
TGValueTypes.cpp
X86DisassemblerShared.h
X86DisassemblerTables.cpp
X86DisassemblerTables.h
X86ModRMFilters.cpp
X86ModRMFilters.h
X86RecognizableInstr.cpp	X86: add GATHER intrinsics (AVX2) in LLVM	2012-06-26 19:47:59 +00:00
X86RecognizableInstr.h