John Brawn 272d7fdf42 [ARM] Add support for -sp- FPUs and FPU none to TargetParser ... These are added mainly for the benefit of clang, but this also means that they are now allowed in .fpu directives and we emit the correct .fpu directive when single-precision-only is used. Differential Revision: http://reviews.llvm.org/D10238 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239151 91177308-0d34-0410-b5e6-96231b3b80d8		2015-06-05 13:31:19 +00:00
..
AArch64	[GlobalMerge] Take into account minsize on Global users' parents.	2015-06-04 20:39:23 +00:00
ARM	[ARM] Add support for -sp- FPUs and FPU none to TargetParser	2015-06-05 13:31:19 +00:00
BPF	[bpf] add big- and host- endian support	2015-06-04 19:15:05 +00:00
CPP
Generic	Resubmit r237954 (MIR Serialization: print and parse LLVM IR using MIR format).	2015-05-27 18:02:19 +00:00
Hexagon	Shouldn't be XFAIL'ed.	2015-06-04 21:49:43 +00:00
Inputs
Mips	[mips] Make TTypeEncoding indirect to allow .eh_frame to be read-only.	2015-06-02 20:32:50 +00:00
MIR	MIR Serialization: use correct line and column numbers for LLVM IR errors.	2015-05-29 17:05:41 +00:00
MSP430
NVPTX	[NVPTX] roll forward r239082	2015-06-04 21:28:26 +00:00
PowerPC	Add support for VSX FMA single-precision instructions to the PPC back end	2015-05-29 17:13:25 +00:00
R600	R600/SI: Reimplement isLegalAddressingMode	2015-06-04 16:17:42 +00:00
SPARC
SystemZ
Thumb	Thumb2: Modify codegen for memcpy intrinsic to prefer LDM/STM.	2015-05-28 20:02:45 +00:00
Thumb2	ARM: Thumb2 LDRD/STRD supports independent input/output regs	2015-06-03 16:30:24 +00:00
WinEH
X86	[X86][AVX2] Added tests for v32i8 vector shifts	2015-06-05 12:35:36 +00:00
XCore