Toma Tabacu 279a212ca2 [mips] [IAS] Add support for the B{L,G}{T,E}(U) branch pseudo-instructions. ... Summary: This does not include support for the immediate variants of these pseudo-instructions. Fixes llvm.org/PR20968. Reviewers: dsanders Reviewed By: dsanders Subscribers: seanbruno, emaste, llvm-commits Differential Revision: http://reviews.llvm.org/D8537 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239905 91177308-0d34-0410-b5e6-96231b3b80d8		2015-06-17 13:20:24 +00:00
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AArch64	[AArch64] AsmParser should be case insensitive about accepting vector register names.	2015-06-08 21:32:16 +00:00
AMDGPU	R600 -> AMDGPU rename	2015-06-13 03:28:10 +00:00
ARM	[ARM] Add support for -sp- FPUs and FPU none to TargetParser	2015-06-05 13:31:19 +00:00
AsmParser	Teaching llvm-mc how to understand the defsym command line option. This allows integer-constant symbols to be defined on the command line and used during assembly.	2015-06-07 01:46:24 +00:00
COFF
Disassembler	[mips][microMIPS] Implement ERET and ERETNC instructions	2015-06-11 10:22:46 +00:00
ELF	Fix a regression in .pop_section.	2015-06-08 20:08:55 +00:00
Hexagon	[Hexagon] Reapply r239097 with tests corrected for shuffling and duplexing.	2015-06-05 16:00:11 +00:00
MachO
Markup
Mips	[mips] [IAS] Add support for the B{L,G}{T,E}(U) branch pseudo-instructions.	2015-06-17 13:20:24 +00:00
PowerPC	Properly handle the mftb instruction.	2015-06-16 16:01:15 +00:00
Sparc	[llvm-mc] The object form of the GNU triple should be the same as the string form.	2015-06-16 09:57:38 +00:00
SystemZ
X86	Add support for parsing the XOR operator in Intel syntax inline assembly.	2015-06-14 12:59:45 +00:00