llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-15 07:34:33 +00:00

History

Jim Grosbach 280dfad489 ARM VLD parsing and encoding.

Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.

Adjust the instruction definitions to only have the single encoded register
as an operand. The super-register from the pseudo is kept as an implicit def,
so passes which come after pseudo-expansion still know that the instruction
defines the other subregs.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142670 91177308-0d34-0410-b5e6-96231b3b80d8

2011-10-21 18:54:25 +00:00

ARM

ARM VLD parsing and encoding.

2011-10-21 18:54:25 +00:00

AsmParser

Fix parsing of a line with only a # in it.

2011-10-19 18:48:52 +00:00

COFF

…

Disassembler

Revert r142618, r142622, and r142624, which were based on an incorrect reading of the ARMv7 docs.

2011-10-20 22:23:58 +00:00