Jim Grosbach 280dfad489 ARM VLD parsing and encoding. ... Next step in the ongoing saga of NEON load/store assmebly parsing. Handle VLD1 instructions that take a two-register register list. Adjust the instruction definitions to only have the single encoded register as an operand. The super-register from the pseudo is kept as an implicit def, so passes which come after pseudo-expansion still know that the instruction defines the other subregs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142670 91177308-0d34-0410-b5e6-96231b3b80d8		2011-10-21 18:54:25 +00:00
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ARM	ARM VLD parsing and encoding.	2011-10-21 18:54:25 +00:00
AsmParser	Fix parsing of a line with only a # in it.	2011-10-19 18:48:52 +00:00
COFF	Add the suffix to the Win64 EH data sections' names if given. Add a test for	2011-05-27 21:38:47 +00:00
Disassembler	Revert r142618, r142622, and r142624, which were based on an incorrect reading of the ARMv7 docs.	2011-10-20 22:23:58 +00:00
ELF	Apparently, sometimes llvm-nm doesn't put the undefined symbol at the top. Take	2011-10-11 06:58:11 +00:00
MachO	Fix a Darwin x86_64 special case of a jmp to a temporary symbol from an atom	2011-09-08 20:53:44 +00:00
MBlaze
X86	Rename PEXTR to PEXT. Add intrinsics for BMI instructions.	2011-10-19 07:48:35 +00:00