Juergen Ributzka c7e77f91fe SelectionDAG: Teach the legalizer to split SETCC if VSELECT needs splitting too. ... This patch reapplies r193676 with an additional fix for the Hexagon backend. The SystemZ backend has already been fixed by r194148. The Type Legalizer recognizes that VSELECT needs to be split, because the type is to wide for the given target. The same does not always apply to SETCC, because less space is required to encode the result of a comparison. As a result VSELECT is split and SETCC is unrolled into scalar comparisons. This commit fixes the issue by checking for VSELECT-SETCC patterns in the DAG Combiner. If a matching pattern is found, then the result mask of SETCC is promoted to the expected vector mask type for the given target. Now the type legalizer will split both VSELECT and SETCC. This allows the following X86 DAG Combine code to sucessfully detect the MIN/MAX pattern. This fixes PR16695, PR17002, and <rdar://problem/14594431>. Reviewed by Nadav git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194542 91177308-0d34-0410-b5e6-96231b3b80d8		2013-11-13 01:57:54 +00:00
..
InstPrinter
MCTargetDesc	Add a MCAsmInfoELF class and factor some code into it.	2013-10-16 01:34:32 +00:00
TargetInfo
CMakeLists.txt
Hexagon.h
Hexagon.td
HexagonAsmPrinter.cpp	Add a helper getSymbol to AsmPrinter.	2013-10-29 17:07:16 +00:00
HexagonAsmPrinter.h
HexagonCallingConv.td
HexagonCallingConvLower.cpp
HexagonCallingConvLower.h
HexagonCFGOptimizer.cpp
HexagonCopyToCombine.cpp
HexagonExpandPredSpillCode.cpp
HexagonFixupHwLoops.cpp
HexagonFrameLowering.cpp
HexagonFrameLowering.h
HexagonHardwareLoops.cpp	Replace some unnecessary vector copies with references.	2013-09-15 22:04:42 +00:00
HexagonInstrFormats.td	Even more spelling fixes for "instruction".	2013-09-28 13:42:22 +00:00
HexagonInstrFormatsV4.td
HexagonInstrInfo.cpp
HexagonInstrInfo.h
HexagonInstrInfo.td
HexagonInstrInfoV3.td
HexagonInstrInfoV4.td	Prune trailing linefeeds.	2013-10-28 04:07:31 +00:00
HexagonInstrInfoV5.td
HexagonIntrinsics.td
HexagonIntrinsicsDerived.td
HexagonIntrinsicsV3.td
HexagonIntrinsicsV4.td
HexagonIntrinsicsV5.td
HexagonISelDAGToDAG.cpp	ISelDAG: spot chain cycles involving MachineNodes	2013-09-22 08:21:56 +00:00
HexagonISelLowering.cpp	Hexagon: Remove global state.	2013-10-27 11:16:09 +00:00
HexagonISelLowering.h	SelectionDAG: Teach the legalizer to split SETCC if VSELECT needs splitting too.	2013-11-13 01:57:54 +00:00
HexagonMachineFunctionInfo.h
HexagonMachineScheduler.cpp	Rename variables for consistency.	2013-09-11 00:41:02 +00:00
HexagonMachineScheduler.h	mi-sched: Precompute a PressureDiff for each instruction, adjust for liveness later.	2013-08-30 03:49:48 +00:00
HexagonMCInstLower.cpp	Add a helper getSymbol to AsmPrinter.	2013-10-29 17:07:16 +00:00
HexagonNewValueJump.cpp
HexagonOperands.td
HexagonPeephole.cpp	Even more spelling fixes for "instruction".	2013-09-28 13:42:22 +00:00
HexagonRegisterInfo.cpp	Remove getEHExceptionRegister and getEHHandlerRegister.	2013-10-07 13:39:22 +00:00
HexagonRegisterInfo.h	Remove getEHExceptionRegister and getEHHandlerRegister.	2013-10-07 13:39:22 +00:00
HexagonRegisterInfo.td
HexagonRemoveSZExtArgs.cpp
HexagonSchedule.td
HexagonScheduleV4.td
HexagonSelectCCInfo.td
HexagonSelectionDAGInfo.cpp
HexagonSelectionDAGInfo.h
HexagonSplitConst32AndConst64.cpp
HexagonSplitTFRCondSets.cpp
HexagonSubtarget.cpp
HexagonSubtarget.h
HexagonTargetMachine.cpp	Allow subtarget selection of the default MachineScheduler and document the interface.	2013-09-20 05:14:41 +00:00
HexagonTargetMachine.h
HexagonTargetObjectFile.cpp
HexagonTargetObjectFile.h
HexagonVarargsCallingConvention.h
HexagonVLIWPacketizer.cpp
LLVMBuild.txt
Makefile