Jakob Stoklund Olesen 2afb7505c5 Teach VirtRegRewriter to handle spilling in instructions that have multiple ... definitions of the virtual register. This happens when spilling the registers produced by REG_SEQUENCE: %reg1047:5<def>, %reg1047:6<def>, %reg1047:7<def> = VLD3d8 %reg1033, 0, pred:14, pred:%reg0 The rewriter would spill the register multiple times, dead store elimination tried to keep up, but ended up cutting the branch it was sitting on. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104321 91177308-0d34-0410-b5e6-96231b3b80d8		2010-05-21 16:36:13 +00:00
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Alpha
ARM	Teach VirtRegRewriter to handle spilling in instructions that have multiple	2010-05-21 16:36:13 +00:00
Blackfin
CBackend
CellSPU
CPP
Generic
MBlaze
Mips
MSP430
PIC16
PowerPC	Only use clairvoyance when defining a register, and then only if it has one use.	2010-05-17 04:50:57 +00:00
SPARC
SystemZ	SystemZ really does mean "has calls" and not just "adjusts stack." Go ahead and	2010-05-14 22:17:42 +00:00
Thumb
Thumb2	t2LEApcrel and tLEApcrel are re-materializable. This makes it possible to hoist more loads during machine LICM.	2010-05-19 07:28:01 +00:00
X86	Fix i64->f64 conversion, x86-64, -no-sse. A bit	2010-05-21 00:52:33 +00:00
XCore