Files
llvm-6502/test/CodeGen/ARM
Jakob Stoklund Olesen 2afb7505c5 Teach VirtRegRewriter to handle spilling in instructions that have multiple
definitions of the virtual register.

This happens when spilling the registers produced by REG_SEQUENCE:

%reg1047:5<def>, %reg1047:6<def>, %reg1047:7<def> = VLD3d8 %reg1033, 0, pred:14, pred:%reg0

The rewriter would spill the register multiple times, dead store elimination
tried to keep up, but ended up cutting the branch it was sitting on.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104321 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 16:36:13 +00:00
..
2010-03-06 19:39:36 +00:00
2010-01-19 00:35:20 +00:00
2010-05-05 21:07:46 +00:00
2010-03-14 18:42:52 +00:00
2010-04-17 16:29:15 +00:00
2010-04-17 16:29:15 +00:00
2010-02-08 23:47:34 +00:00
2009-10-21 08:15:52 +00:00
2010-01-05 17:55:26 +00:00
2009-11-17 20:38:36 +00:00
2009-09-24 20:23:02 +00:00
2009-09-15 20:58:02 +00:00
2009-09-15 20:58:02 +00:00
2009-10-07 20:51:42 +00:00