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llvm-6502/test/CodeGen/ARM
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Jakob Stoklund Olesen 2afb7505c5 Teach VirtRegRewriter to handle spilling in instructions that have multiple 
definitions of the virtual register.

This happens when spilling the registers produced by REG_SEQUENCE:

%reg1047:5<def>, %reg1047:6<def>, %reg1047:7<def> = VLD3d8 %reg1033, 0, pred:14, pred:%reg0

The rewriter would spill the register multiple times, dead store elimination
tried to keep up, but ended up cutting the branch it was sitting on.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104321 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 16:36:13 +00:00
..
2006-11-10-CycleInDAG.ll
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2007-01-19-InfiniteLoop.ll
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2007-03-07-CombinerCrash.ll
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2007-03-13-InstrSched.ll
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2007-03-21-JoinIntervalsCrash.ll
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2007-03-26-RegScavengerAssert.ll
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2007-03-27-RegScavengerAssert.ll
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2007-03-30-RegScavengerAssert.ll
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2007-04-02-RegScavengerAssert.ll
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2007-04-03-PEIBug.ll
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2007-04-03-UndefinedSymbol.ll
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2007-04-30-CombinerCrash.ll
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2007-05-03-BadPostIndexedLd.ll
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2007-05-07-jumptoentry.ll
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2007-05-07-tailmerge-1.ll
Remove the -enable-sjlj-eh option, which doesn't do anything.
2010-05-02 15:36:26 +00:00
2007-05-09-tailmerge-2.ll
Remove the -enable-sjlj-eh option, which doesn't do anything.
2010-05-02 15:36:26 +00:00
2007-05-14-InlineAsmCstCrash.ll
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2007-05-14-RegScavengerAssert.ll
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2007-05-22-tailmerge-3.ll
Remove the -enable-sjlj-eh option, which doesn't do anything.
2010-05-02 15:36:26 +00:00
2007-05-23-BadPreIndexedStore.ll
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2007-05-31-RegScavengerInfiniteLoop.ll
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2007-08-15-ReuseBug.ll
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2008-02-04-LocalRegAllocBug.ll
Keep track of the last place a live virtreg was used.
2010-05-11 23:24:45 +00:00
2008-02-29-RegAllocLocal.ll
Keep track of the last place a live virtreg was used.
2010-05-11 23:24:45 +00:00
2008-03-05-SxtInRegBug.ll
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2008-03-07-RegScavengerAssert.ll
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2008-04-04-ScavengerAssert.ll
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2008-04-10-ScavengerAssert.ll
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2008-04-11-PHIofImpDef.ll
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2008-05-19-LiveIntervalsBug.ll
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2008-05-19-ScavengerAssert.ll
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2008-07-17-Fdiv.ll
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2008-07-24-CodeGenPrepCrash.ll
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2008-08-07-AsmPrintBug.ll
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2008-09-14-CoalescerBug.ll
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2008-09-17-CoalescerBug.ll
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2008-11-18-ScavengerAssert.ll
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2009-02-16-SpillerBug.ll
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2009-02-22-SoftenFloatVaArg.ll
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2009-02-27-SpillerBug.ll
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2009-03-07-SpillerBug.ll
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2009-03-09-AddrModeBug.ll
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2009-04-06-AsmModifier.ll
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2009-04-08-AggregateAddr.ll
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2009-04-08-FloatUndef.ll
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2009-04-08-FREM.ll
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2009-04-09-RegScavengerAsm.ll
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2009-05-05-DAGCombineBug.ll
Correct some bogus target triples.
2010-05-07 17:03:48 +00:00
2009-05-07-RegAllocLocal.ll
Keep track of the last place a live virtreg was used.
2010-05-11 23:24:45 +00:00
2009-05-11-CodePlacementCrash.ll
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2009-05-18-InlineAsmMem.ll
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2009-06-02-ISelCrash.ll
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2009-06-04-MissingLiveIn.ll
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2009-06-12-RegScavengerAssert.ll
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2009-06-15-RegScavengerAssert.ll
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2009-06-19-RegScavengerAssert.ll
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2009-06-22-CoalescerBug.ll
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2009-06-30-RegScavengerAssert2.ll
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2009-06-30-RegScavengerAssert3.ll
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2009-06-30-RegScavengerAssert4.ll
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2009-06-30-RegScavengerAssert5.ll
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2009-06-30-RegScavengerAssert.ll
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2009-07-01-CommuteBug.ll
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2009-07-09-asm-p-constraint.ll
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2009-07-18-RewriterBug.ll
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2009-07-22-ScavengerAssert.ll
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2009-07-22-SchedulerAssert.ll
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2009-07-29-VFP3Registers.ll
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2009-08-02-RegScavengerAssert-Neon.ll
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2009-08-04-RegScavengerAssert-2.ll
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2009-08-04-RegScavengerAssert.ll
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2009-08-15-RegScavenger-EarlyClobber.ll
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2009-08-15-RegScavengerAssert.ll
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2009-08-21-PostRAKill2.ll
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2009-08-21-PostRAKill3.ll
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2009-08-21-PostRAKill4.ll
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2009-08-21-PostRAKill.ll
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2009-08-23-linkerprivate.ll
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2009-08-26-ScalarToVector.ll
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2009-08-27-ScalarToVector.ll
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2009-08-29-ExtractEltf32.ll
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2009-08-29-TooLongSplat.ll
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2009-08-31-LSDA-Name.ll
Start function numbering at 0.
2010-04-17 16:29:15 +00:00
2009-08-31-TwoRegShuffle.ll
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2009-09-01-PostRAProlog.ll
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2009-09-09-AllOnes.ll
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2009-09-09-fpcmp-ole.ll
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2009-09-10-postdec.ll
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2009-09-13-InvalidSubreg.ll
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2009-09-13-InvalidSuperReg.ll
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2009-09-20-LiveIntervalsBug.ll
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2009-09-21-LiveVariablesBug.ll
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2009-09-22-LiveVariablesBug.ll
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2009-09-23-LiveVariablesBug.ll
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2009-09-24-spill-align.ll
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2009-09-27-CoalescerBug.ll
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2009-09-28-LdStOptiBug.ll
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2009-10-02-NEONSubregsBug.ll
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2009-10-21-InvalidFNeg.ll
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2009-10-27-double-align.ll
Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrm
2010-03-17 17:52:21 +00:00
2009-10-30.ll
Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrm
2010-03-17 17:52:21 +00:00
2009-11-01-NeonMoves.ll
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2009-11-02-NegativeLane.ll
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2009-11-07-SubRegAsmPrinting.ll
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2009-11-13-CoalescerCrash.ll
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2009-11-13-ScavengerAssert2.ll
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2009-11-13-ScavengerAssert.ll
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2009-11-13-VRRewriterCrash.ll
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2009-11-30-LiveVariablesBug.ll
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2009-12-02-vtrn-undef.ll
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2010-03-04-eabi-fp-spill.ll
pr6478: The frame pointer spill frame index is only defined when there is a
2010-03-04 21:42:36 +00:00
2010-03-04-stm-undef-addr.ll
pr6480: Don't try producing ld/st-multiple instructions when the address is
2010-03-04 21:04:38 +00:00
2010-03-18-ldm-rtrn.ll
pr6652: Use LDM to restore PC to the return address on ARMv4.
2010-03-20 22:20:40 +00:00
2010-04-07-DbgValueOtherTargets.ll
Split big test into multiple directories to cater to
2010-04-07 20:43:35 +00:00
2010-04-09-NeonSelect.ll
Add a testcase for svn r100568.
2010-04-09 18:29:29 +00:00
2010-04-13-v2f64SplitArg.ll
Handle a v2f64 formal parameter that is split between registers and memory
2010-04-13 22:03:22 +00:00
2010-04-14-SplitVector.ll
Don't custom lower bit converts to ARM VMOVDRRD or VMOVDRR when the operand
2010-04-14 20:45:23 +00:00
2010-04-15-ScavengerDebugValue.ll
Fix PR6847. RegScavenger should ignore DebugValues.
2010-04-15 20:28:39 +00:00
2010-05-14-IllegalType.ll
Allow TargetLowering::getRegClassFor() to be called on illegal types. Also
2010-05-15 02:18:07 +00:00
2010-05-17-DAGCombineAssert.ll
FIX PR7158. SimplifyVBinOp was asserting when it fails to constant fold (op (build_vector), (build_vector)).
2010-05-18 00:03:40 +00:00
2010-05-17-FastAllocCrash.ll
Avoid allocating the same physreg to multiple virtregs in one instruction.
2010-05-17 17:18:59 +00:00
2010-05-18-LocalAllocCrash.ll
Remember to update VirtRegLastUse when spilling without killing before a call.
2010-05-18 22:20:09 +00:00
2010-05-18-PostIndexBug.ll
Sink dag combine's post index load / store code that swap base ptr and index into the target hook. Only the target knows whether the swap is safe. In Thumb2 mode, the offset must be an immediate. rdar://7998649
2010-05-18 21:31:17 +00:00
2010-05-19-Shuffles.ll
Handle Neon v2f64 and v2i64 vector shuffles as register copies.
2010-05-20 18:39:53 +00:00
2010-05-20-NEONSpillCrash.ll
Teach VirtRegRewriter to handle spilling in instructions that have multiple
2010-05-21 16:36:13 +00:00
addrmode.ll
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aliases.ll
emit jump table an alias ".set" directives through MCStreamer as
2010-01-26 21:53:08 +00:00
align.ll
Emit .comm alignment in bytes but .align in powers of 2 for ARM ELF.
2010-01-26 20:21:43 +00:00
alloca.ll
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argaddr.ll
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arguments2.ll
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arguments3.ll
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arguments4.ll
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arguments5.ll
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arguments6.ll
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arguments7.ll
Fix declarations in a few more tests.
2010-04-17 21:29:25 +00:00
arguments8.ll
Fix declarations in a few more tests.
2010-04-17 21:29:25 +00:00
arguments_f64_backfill.ll
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arguments-nosplit-double.ll
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arguments-nosplit-i64.ll
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arguments.ll
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arm-asm.ll
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arm-frameaddr.ll
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arm-negative-stride.ll
Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrm
2010-03-17 17:52:21 +00:00
armv4.ll
Initial bits of ARMv4-only support.
2010-03-06 19:39:36 +00:00
bfc.ll
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bfx.ll
Update ARM DAGtoDAG for matching UBFX instruction for unsigned bitfield
2010-04-22 23:24:18 +00:00
bic.ll
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bits.ll
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bx_fold.ll
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call_nolink.ll
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call.ll
Fix pr6111: Avoid using the LR register for the target address of an indirect
2010-02-16 17:24:15 +00:00
carry.ll
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clz.ll
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compare-call.ll
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constants.ll
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cse-libcalls.ll
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ctors_dtors.ll
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ctz.ll
Test case for r93758.
2010-01-19 00:35:20 +00:00
dg.exp
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div.ll
fix copy/paste oops.
2010-05-05 21:07:46 +00:00
dyn-stackalloc.ll
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extloadi1.ll
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fabss.ll
Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float).
2010-05-21 00:43:17 +00:00
fadds.ll
Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float).
2010-05-21 00:43:17 +00:00
fcopysign.ll
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fdivs.ll
Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float).
2010-05-21 00:43:17 +00:00
fixunsdfdi.ll
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fmacs.ll
Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float).
2010-05-21 00:43:17 +00:00
fmdrr-fmrrd.ll
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fmscs.ll
Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float).
2010-05-21 00:43:17 +00:00
fmuls.ll
Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float).
2010-05-21 00:43:17 +00:00
fnegs.ll
switch the flag for using NEON for SP floating point to a subtarget 'feature'.
2010-03-25 23:47:34 +00:00
fnmacs.ll
switch the flag for using NEON for SP floating point to a subtarget 'feature'.
2010-03-25 23:47:34 +00:00
fnmscs.ll
Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float).
2010-05-21 00:43:17 +00:00
fnmul.ll
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fnmuls.ll
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formal.ll
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fp16.ll
Fix typo
2010-03-14 18:42:52 +00:00
fp_convert.ll
switch the flag for using NEON for SP floating point to a subtarget 'feature'.
2010-03-25 23:47:34 +00:00
fp.ll
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fparith.ll
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fpcmp_ueq.ll
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fpcmp.ll
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fpconsts.ll
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fpconv.ll
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fpmem.ll
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fpow.ll
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fpowi.ll
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fptoint.ll
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fsubs.ll
switch the flag for using NEON for SP floating point to a subtarget 'feature'.
2010-03-25 23:47:34 +00:00
globals.ll
Start function numbering at 0.
2010-04-17 16:29:15 +00:00
hardfloat_neon.ll
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hello.ll
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hidden-vis-2.ll
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hidden-vis-3.ll
Start function numbering at 0.
2010-04-17 16:29:15 +00:00
hidden-vis.ll
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iabs.ll
convert to filecheck.
2010-02-08 23:47:34 +00:00
ifcvt1.ll
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ifcvt2.ll
Fix a bug which prevented tail merging of return instructions in
2010-05-03 14:35:47 +00:00
ifcvt3.ll
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ifcvt4.ll
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ifcvt5.ll
Fix a bug which prevented tail merging of return instructions in
2010-05-03 14:35:47 +00:00
ifcvt6.ll
Stop using the old pre-UAL syntax for LDM/STM instruction suffixes.
2010-03-16 16:19:07 +00:00
ifcvt7.ll
Stop using the old pre-UAL syntax for LDM/STM instruction suffixes.
2010-03-16 16:19:07 +00:00
ifcvt8.ll
Stop using the old pre-UAL syntax for LDM/STM instruction suffixes.
2010-03-16 16:19:07 +00:00
ifcvt9.ll
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illegal-vector-bitcast.ll
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imm.ll
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indirectbr.ll
fix AsmPrinter::GetBlockAddressSymbol to always return a unique
2010-03-14 17:53:23 +00:00
inlineasm2.ll
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inlineasm3.ll
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inlineasm-imm-arm.ll
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inlineasm.ll
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insn-sched1.ll
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ispositive.ll
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large-stack.ll
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ldm.ll
Stop using the old pre-UAL syntax for LDM/STM instruction suffixes.
2010-03-16 16:19:07 +00:00
ldr_ext.ll
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ldr_frame.ll
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ldr_post.ll
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ldr_pre.ll
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ldr.ll
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ldrd.ll
Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrm
2010-03-17 17:52:21 +00:00
load.ll
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long_shift.ll
Run codegen dce pass for all targets at all optimization levels. Previously it's
2010-02-06 09:07:11 +00:00
long-setcc.ll
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long.ll
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lsr-code-insertion.ll
Reapply the new LoopStrengthReduction code, with compile time and
2010-02-12 10:34:29 +00:00
lsr-on-unrolled-loops.ll
When canonicalizing icmp operand order to put the loop invariant
2010-05-20 19:26:52 +00:00
lsr-scale-addr-mode.ll
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mem.ll
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memcpy-inline.ll
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memfunc.ll
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mls.ll
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movt-movw-global.ll
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movt.ll
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mul_const.ll
Some cheap DAG combine goodness for multiplication with a particular constant.
2010-05-15 18:16:59 +00:00
mul.ll
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mulhi.ll
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mvn.ll
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neon_arith1.ll
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neon_ld1.ll
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neon_ld2.ll
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neon_minmax.ll
Check for comparisons of +/- zero when optimizing less-than-or-equal and
2010-02-24 22:15:53 +00:00
pack.ll
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pr3502.ll
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private.ll
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reg_sequence.ll
Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float).
2010-05-21 00:43:17 +00:00
remat.ll
Delete dead PHI machine instructions. These can be created due to type
2010-02-10 22:58:57 +00:00
ret0.ll
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ret_arg1.ll
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ret_arg2.ll
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ret_arg3.ll
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ret_arg4.ll
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ret_arg5.ll
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ret_f32_arg2.ll
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ret_f32_arg5.ll
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ret_f64_arg2.ll
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ret_f64_arg_reg_split.ll
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ret_f64_arg_split.ll
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ret_f64_arg_stack.ll
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ret_i64_arg2.ll
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ret_i64_arg3.ll
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ret_i64_arg_split.ll
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ret_i128_arg2.ll
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ret_void.ll
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rev.ll
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sbfx.ll
add a simple dag combine to replace trivial shl+lshr with
2010-04-15 05:28:43 +00:00
section.ll
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select_xform.ll
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select-imm.ll
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select.ll
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shifter_operand.ll
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smul.ll
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spill-q.ll
…
stack-frame.ll
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stm.ll
…
str_post.ll
…
str_pre-2.ll
Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrm
2010-03-17 17:52:21 +00:00
str_pre.ll
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str_trunc.ll
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sxt_rot.ll
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t2-imm.ll
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tail-opts.ll
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thread_pointer.ll
…
tls1.ll
…
tls2.ll
Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrm
2010-03-17 17:52:21 +00:00
tls3.ll
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trap.ll
Select @llvm.trap to the special B with 1111 condition (i.e. trap) instruction.
2010-05-11 07:26:32 +00:00
trunc_ldr.ll
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truncstore-dag-combine.ll
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tst_teq.ll
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uint64tof64.ll
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unaligned_load_store.ll
Fix a gross typo: ARMv6+ may or may not support unaligned memory operations.
2010-01-30 14:08:12 +00:00
unord.ll
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uxt_rot.ll
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uxtb.ll
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vaba.ll
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vabd.ll
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vabs.ll
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vadd.ll
Fix tests to use fadd, fsub, and fmul, instead of add, sub, and mul,
2010-05-03 22:36:46 +00:00
vargs_align.ll
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vargs.ll
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vbits.ll
The Neon "vtst" instruction takes a suffix that is the element size alone --
2010-01-17 06:35:17 +00:00
vbsl.ll
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vceq.ll
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vcge.ll
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vcgt.ll
Intrinsics which do a vector compare (results are all zero or all ones) are modeled as icmp / fcmp + sext. This is turned into a vsetcc by dag combine (yes, not a good long term solution). The targets can then isel the vsetcc to the appropriate instruction.
2010-05-19 01:08:17 +00:00
vcnt.ll
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vcombine.ll
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vcvt.ll
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vdup.ll
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vext.ll
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vfcmp.ll
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vfp.ll
…
vget_lane.ll
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vhadd.ll
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vhsub.ll
…
vicmp.ll
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vld1.ll
Fix tests for Neon load/store intrinsics to match the i8* types expected by
2010-04-20 00:17:16 +00:00
vld2.ll
Fix tests to use fadd, fsub, and fmul, instead of add, sub, and mul,
2010-05-03 22:36:46 +00:00
vld3.ll
Fix tests to use fadd, fsub, and fmul, instead of add, sub, and mul,
2010-05-03 22:36:46 +00:00
vld4.ll
Fix tests to use fadd, fsub, and fmul, instead of add, sub, and mul,
2010-05-03 22:36:46 +00:00
vldlane.ll
Fix tests to use fadd, fsub, and fmul, instead of add, sub, and mul,
2010-05-03 22:36:46 +00:00
vminmax.ll
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vmla.ll
Fix tests to use fadd, fsub, and fmul, instead of add, sub, and mul,
2010-05-03 22:36:46 +00:00
vmls.ll
Fix tests to use fadd, fsub, and fmul, instead of add, sub, and mul,
2010-05-03 22:36:46 +00:00
vmov.ll
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vmul.ll
Fix tests to use fadd, fsub, and fmul, instead of add, sub, and mul,
2010-05-03 22:36:46 +00:00
vneg.ll
Fix tests to use fadd, fsub, and fmul, instead of add, sub, and mul,
2010-05-03 22:36:46 +00:00
vpadal.ll
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vpadd.ll
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vpminmax.ll
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vqadd.ll
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vqdmul.ll
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vqshl.ll
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vqshrn.ll
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vqsub.ll
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vrec.ll
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vrev.ll
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vshift.ll
…
vshiftins.ll
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vshl.ll
…
vshll.ll
…
vshrn.ll
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vsra.ll
…
vst1.ll
Fix tests for Neon load/store intrinsics to match the i8* types expected by
2010-04-20 00:17:16 +00:00
vst2.ll
Fix tests for Neon load/store intrinsics to match the i8* types expected by
2010-04-20 00:17:16 +00:00
vst3.ll
Fix tests for Neon load/store intrinsics to match the i8* types expected by
2010-04-20 00:17:16 +00:00
vst4.ll
Fix tests for Neon load/store intrinsics to match the i8* types expected by
2010-04-20 00:17:16 +00:00
vstlane.ll
Fix tests for Neon load/store intrinsics to match the i8* types expected by
2010-04-20 00:17:16 +00:00
vsub.ll
Fix tests to use fadd, fsub, and fmul, instead of add, sub, and mul,
2010-05-03 22:36:46 +00:00
vtbl.ll
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vtrn.ll
Fix tests to use fadd, fsub, and fmul, instead of add, sub, and mul,
2010-05-03 22:36:46 +00:00
vuzp.ll
Fix tests to use fadd, fsub, and fmul, instead of add, sub, and mul,
2010-05-03 22:36:46 +00:00
vzip.ll
Fix tests to use fadd, fsub, and fmul, instead of add, sub, and mul,
2010-05-03 22:36:46 +00:00
weak2.ll
…
weak.ll
…