llvm-6502/test/CodeGen/R600
Matt Arsenault 746734df1a R600/SI: Try to use scalar BFE.
Use scalar BFE with constant shift and offset when possible.
This is complicated by the fact that the scalar version packs
the two operands of the vector version into one.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206558 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-18 05:19:26 +00:00
..
32-bit-local-address-space.ll R600/SI: Print more immediates in hex format 2014-04-15 22:32:49 +00:00
64bit-kernel-args.ll R600/SI: Print more immediates in hex format 2014-04-15 22:32:49 +00:00
128bit-kernel-args.ll
add_i64.ll R600: Implement isZExtFree. 2014-03-27 17:23:31 +00:00
add.ll
address-space.ll R600/SI: Print more immediates in hex format 2014-04-15 22:32:49 +00:00
and.ll
anyext.ll
array-ptr-calc-i32.ll
array-ptr-calc-i64.ll
atomic_load_add.ll
atomic_load_sub.ll
basic-branch.ll
basic-loop.ll
bfe_uint.ll
bfi_int.ll
big_alu.ll
bitcast.ll
build_vector.ll
call_fs.ll
cayman-loop-bug.ll
cf_end.ll
cf-stack-bug.ll
codegen-prepare-addrmode-sext.ll
combine_vloads.ll
complex-folding.ll
dagcombiner-bug-illegal-vec4-int-to-fp.ll
disconnected-predset-break-bug.ll
dot4-folding.ll
elf.ll
elf.r600.ll
extload.ll R600/SI: Use SReg_64 instead of VSrc_64 when selecting BUILD_PAIR 2014-04-18 00:36:21 +00:00
fabs.ll
fadd64.ll
fadd.ll
fceil.ll
fcmp64.ll
fcmp-cnd.ll
fcmp-cnde-int-args.ll
fcmp.ll
fconst64.ll R600/SI: Print more immediates in hex format 2014-04-15 22:32:49 +00:00
fdiv64.ll
fdiv.ll
fetch-limits.r600.ll
fetch-limits.r700+.ll
ffloor.ll
floor.ll
fma.ll
fmad.ll
fmax.ll
fmin.ll
fmul64.ll
fmul.ll
fmuladd.ll
fneg-fabs.ll
fneg.ll
fp64_to_sint.ll
fp_to_sint.ll
fp_to_uint.ll
fpext.ll
fptrunc.ll
fsqrt.ll
fsub64.ll
fsub.ll
ftrunc.ll
gep-address-space.ll R600/SI: Print more immediates in hex format 2014-04-15 22:32:49 +00:00
gv-const-addrspace.ll
i8-to-double-to-float.ll
icmp64.ll
icmp-select-sete-reverse-args.ll
imm.ll
indirect-addressing-si.ll
indirect-private-64.ll R600/SI: Fix 64-bit private loads. 2014-03-24 17:50:46 +00:00
infinite-loop-evergreen.ll
infinite-loop.ll R600/SI: Print more immediates in hex format 2014-04-15 22:32:49 +00:00
insert_vector_elt_f64.ll
insert_vector_elt.ll R600/SI: Handle INSERT_SUBREG in SIFixSGPRCopies 2014-04-07 19:45:45 +00:00
jump-address.ll
kcache-fold.ll
kernel-args.ll R600/SI: Print more immediates in hex format 2014-04-15 22:32:49 +00:00
lds-oqap-crash.ll
lds-output-queue.ll
lds-size.ll
legalizedag-bug-expand-setcc.ll
lit.local.cfg
literals.ll
llvm.AMDGPU.barrier.local.ll
llvm.AMDGPU.bfe.i32.ll R600: Correct opcode for BFE_INT 2014-04-03 20:19:29 +00:00
llvm.AMDGPU.bfe.u32.ll R600: Add BFE, BFI, and BFM intrinsics to help with writing tests. 2014-03-31 18:21:18 +00:00
llvm.AMDGPU.bfi.ll R600: Add BFE, BFI, and BFM intrinsics to help with writing tests. 2014-03-31 18:21:18 +00:00
llvm.AMDGPU.bfm.ll R600: Add BFE, BFI, and BFM intrinsics to help with writing tests. 2014-03-31 18:21:18 +00:00
llvm.AMDGPU.cube.ll
llvm.AMDGPU.imax.ll R600/SI: Move instruction patterns to scalar versions. 2014-03-21 18:01:18 +00:00
llvm.AMDGPU.imin.ll R600/SI: Move instruction patterns to scalar versions. 2014-03-21 18:01:18 +00:00
llvm.AMDGPU.kill.ll
llvm.AMDGPU.mul.ll
llvm.AMDGPU.tex.ll
llvm.AMDGPU.trunc.ll
llvm.AMDGPU.umax.ll R600: Compute masked bits for min and max 2014-03-31 19:35:33 +00:00
llvm.AMDGPU.umin.ll R600: Compute masked bits for min and max 2014-03-31 19:35:33 +00:00
llvm.cos.ll
llvm.exp2.ll
llvm.floor.ll
llvm.pow.ll
llvm.rint.f64.ll R600/SI: f64 frint is legal on CI 2014-04-17 17:06:37 +00:00
llvm.rint.ll R600/SI: f64 frint is legal on CI 2014-04-17 17:06:37 +00:00
llvm.round.ll
llvm.SI.fs.interp.constant.ll
llvm.SI.imageload.ll
llvm.SI.load.dword.ll
llvm.SI.resinfo.ll
llvm.SI.sample-masked.ll
llvm.SI.sample.ll
llvm.SI.sampled.ll
llvm.SI.sendmsg.ll
llvm.SI.tbuffer.store.ll R600/SI: Print more immediates in hex format 2014-04-15 22:32:49 +00:00
llvm.SI.tid.ll
llvm.sin.ll
llvm.sqrt.ll
llvm.trunc.ll
load64.ll
load-i1.ll R600/SI: Fix loads of i1 2014-04-15 22:28:39 +00:00
load-input-fold.ll
load.ll
load.vec.ll
local-64.ll R600/SI: Print more immediates in hex format 2014-04-15 22:32:49 +00:00
local-memory-two-objects.ll R600/SI: Print more immediates in hex format 2014-04-15 22:32:49 +00:00
local-memory.ll
loop-address.ll
loop-idiom.ll TargetLibraryInfo: Disable memcpy and memset on R600 2014-04-02 19:53:29 +00:00
lshl.ll
lshr.ll
mad_int24.ll R600: Match 24-bit arithmetic patterns in a Target DAGCombine 2014-04-07 19:45:41 +00:00
mad_uint24.ll R600: Match 24-bit arithmetic patterns in a Target DAGCombine 2014-04-07 19:45:41 +00:00
max-literals.ll
mubuf.ll R600/SI: Print more immediates in hex format 2014-04-15 22:32:49 +00:00
mul_int24.ll R600: Match 24-bit arithmetic patterns in a Target DAGCombine 2014-04-07 19:45:41 +00:00
mul_uint24.ll SelectionDAG: Use helper function to improve legalization of ISD::MUL 2014-04-11 16:12:01 +00:00
mul.ll SelectionDAG: Use helper function to improve legalization of ISD::MUL 2014-04-11 16:12:01 +00:00
mulhu.ll R600/SI: Print more immediates in hex format 2014-04-15 22:32:49 +00:00
or.ll R600/SI: Print more immediates in hex format 2014-04-15 22:32:49 +00:00
packetizer.ll
parallelandifcollapse.ll
parallelorifcollapse.ll
predicate-dp4.ll
predicates.ll
private-memory.ll R600/SI: Print more immediates in hex format 2014-04-15 22:32:49 +00:00
pv-packing.ll
pv.ll
r600-encoding.ll
r600-export-fix.ll
r600-infinite-loop-bug-while-reorganizing-vector.ll
r600cfg.ll
README
reciprocal.ll
register-count-comments.ll
rotr.ll
rv7x0_count3.ll
salu-to-valu.ll R600/SI: Handle MUBUF instructions in SIInstrInfo::moveToVALU() 2014-03-21 15:51:57 +00:00
schedule-fs-loop-nested-if.ll
schedule-fs-loop-nested.ll
schedule-fs-loop.ll
schedule-if-2.ll
schedule-if.ll
schedule-vs-if-nested-loop-failure.ll
schedule-vs-if-nested-loop.ll
sdiv.ll
select64.ll R600/SI: Lower i64 SELECT by bitcasting to a vector type 2014-03-31 14:01:55 +00:00
select-vectors.ll
select.ll
selectcc-cnd.ll
selectcc-cnde-int.ll
selectcc-icmp-select-float.ll
selectcc-opt.ll
set-dx10.ll
setcc64.ll
setcc-equivalent.ll Fix missing RUN line in test 2014-04-01 18:34:13 +00:00
setcc.ll
seto.ll
setuo.ll
sext-in-reg.ll R600/SI: Try to use scalar BFE. 2014-04-18 05:19:26 +00:00
sgpr-copy-duplicate-operand.ll
sgpr-copy.ll
shared-op-cycle.ll
shl.ll
si-annotate-cf-assertion.ll
si-lod-bias.ll
si-sgpr-spill.ll
si-vector-hang.ll
sign_extend.ll
sint_to_fp64.ll
sint_to_fp.ll
smrd.ll R600/SI: Print more immediates in hex format 2014-04-15 22:32:49 +00:00
sra.ll
srl.ll
store-v3i32.ll R600: Add failing testcase for <3 x i32> stores. 2014-03-25 16:50:55 +00:00
store-v3i64.ll R600: Add failing testcase for <3 x i32> stores. 2014-03-25 16:50:55 +00:00
store-vector-ptrs.ll
store.ll R600/SI: Stop using i128 as the resource descriptor type 2014-04-17 21:00:11 +00:00
store.r600.ll
structurize1.ll
structurize.ll
sub.ll
swizzle-export.ll
tex-clause-antidep.ll
texture-input-merge.ll
trunc-store-i1.ll R600/SI: Move instruction patterns to scalar versions. 2014-03-21 18:01:18 +00:00
trunc-vector-store-assertion-failure.ll
trunc.ll R600/SI: Print more immediates in hex format 2014-04-15 22:32:49 +00:00
uaddo.ll R600/SI: Fix zext from i1 to i64 2014-04-17 02:03:08 +00:00
udiv.ll
uint_to_fp.ll
unaligned-load-store.ll
unhandled-loop-condition-assertion.ll
unroll.ll
unsupported-cc.ll
urecip.ll
urem.ll
v1i64-kernel-arg.ll
v_cndmask.ll
vertex-fetch-encoding.ll
vselect64.ll
vselect.ll
vtx-fetch-branch.ll
vtx-schedule.ll
wait.ll
work-item-intrinsics.ll R600/SI: Print more immediates in hex format 2014-04-15 22:32:49 +00:00
wrong-transalu-pos-fix.ll
xor.ll R600/SI: Match not instruction. 2014-04-09 07:16:16 +00:00
zero_extend.ll R600/SI: Use SReg_64 instead of VSrc_64 when selecting BUILD_PAIR 2014-04-18 00:36:21 +00:00

+==============================================================================+
| How to organize the lit tests                                                |
+==============================================================================+

- If you write a test for matching a single DAG opcode or intrinsic, it should
  go in a file called {opcode_name,intrinsic_name}.ll (e.g. fadd.ll)

- If you write a test that matches several DAG opcodes and checks for a single
  ISA instruction, then that test should go in a file called {ISA_name}.ll (e.g.
  bfi_int.ll

- For all other tests, use your best judgement for organizing tests and naming
  the files.

+==============================================================================+
| Naming conventions                                                           |
+==============================================================================+

- Use dash '-' and not underscore '_' to separate words in file names, unless
  the file is named after a DAG opcode or ISA instruction that has an
  underscore '_' in its name.