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long %test(ubyte, short, long %X, long %Y) { %A = xor long %X, -1 %B = and long %Y, %A ret long %B } to this: test: save -96, %sp, %sp andn %i4, %i2, %i0 andn %i5, %i3, %i1 restore %g0, %g0, %g0 retl nop instead of this: test: save -96, %sp, %sp xor %i2, -1, %l0 xor %i3, -1, %l1 and %i4, %l0, %i0 and %i5, %l1, %i1 restore %g0, %g0, %g0 retl nop The simpleisel emits: :( test: save -96, %sp, %sp or %g0, -1, %l0 or %g0, -1, %l0 or %g0, -1, %l0 or %g0, -1, %l1 xor %i2, %l0, %l0 xor %i3, %l1, %l1 and %i4, %l0, %i0 and %i5, %l1, %i1 restore %g0, %g0, %g0 retl nop git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24793 91177308-0d34-0410-b5e6-96231b3b80d8 |
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.. | ||
Alpha | ||
CBackend | ||
IA64 | ||
PowerPC | ||
Skeleton | ||
Sparc | ||
SparcV8 | ||
SparcV9 | ||
X86 | ||
Makefile | ||
MRegisterInfo.cpp | ||
SubtargetFeature.cpp | ||
Target.td | ||
TargetData.cpp | ||
TargetFrameInfo.cpp | ||
TargetInstrInfo.cpp | ||
TargetMachine.cpp | ||
TargetMachineRegistry.cpp | ||
TargetSchedInfo.cpp | ||
TargetSchedule.td | ||
TargetSelectionDAG.td | ||
TargetSubtarget.cpp |