Quentin Colombet 30c0f72237 [CodeGenPrepare] Move away sign extensions that get in the way of addressing ... mode. Basically the idea is to transform code like this: %idx = add nsw i32 %a, 1 %sextidx = sext i32 %idx to i64 %gep = gep i8* %myArray, i64 %sextidx load i8* %gep Into: %sexta = sext i32 %a to i64 %idx = add nsw i64 %sexta, 1 %gep = gep i8* %myArray, i64 %idx load i8* %gep That way the computation can be folded into the addressing mode. This transformation is done as part of the addressing mode matcher. If the matching fails (not profitable, addressing mode not legal, etc.), the matcher will revert the related promotions. <rdar://problem/15519855> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200947 91177308-0d34-0410-b5e6-96231b3b80d8		2014-02-06 21:44:56 +00:00
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AArch64	ARM & AArch64: merge NEON absolute compare intrinsics	2014-02-04 14:55:42 +00:00
ARM	Fix PR18345: ldr= pseudo instruction produces incorrect code when using in inline assembly	2014-02-04 17:22:40 +00:00
CPP
Generic	[DAG] Don't pull the binary operation though the shift if the operands have opaque constants.	2014-02-06 04:09:06 +00:00
Hexagon	DebugInfo: Remove some unneeded conditionals now that DIBuilder no longer emits zero-length arrays as {i32 0}	2014-02-04 01:23:52 +00:00
Inputs
Mips	[mips] Add NaCl target and forbid indexed loads and stores for it	2014-02-05 17:19:30 +00:00
MSP430
NVPTX
PowerPC	DebugInfo: Remove some unneeded conditionals now that DIBuilder no longer emits zero-length arrays as {i32 0}	2014-02-04 01:23:52 +00:00
R600	R600/SI: Add a MUBUF store pattern for Reg+Imm offsets	2014-02-06 18:36:41 +00:00
SPARC	[Sparc] Set %o7 as the return address register instead of %i7 in MCRegisterInfo. Also, add CFI instructions to initialize the frame correctly.	2014-02-01 18:54:16 +00:00
SystemZ
Thumb
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X86	[CodeGenPrepare] Move away sign extensions that get in the way of addressing	2014-02-06 21:44:56 +00:00
XCore