llvm-6502/test/CodeGen
Michael Kuperstein 5e343e6fd0 [X86] Improve a dag-combine that handles a vector extract -> zext sequence.
The current DAG combine turns a sequence of extracts from <4 x i32> followed by zexts into a store followed by scalar loads.
According to measurements by Martin Krastev (see PR 21269) for x86-64, a sequence of an extract, movs and shifts gives better performance. However, for 32-bit x86, the previous sequence still seems better.

Differential Revision: http://reviews.llvm.org/D6501

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223360 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-04 13:49:51 +00:00
..
AArch64 AArch64: fix wrong-endian parameter passing. 2014-12-03 17:49:26 +00:00
ARM Emit ABI_FP_rounding attribute. 2014-12-03 08:12:26 +00:00
CPP
Generic
Hexagon
Inputs
Mips [mips] Fix passing of small structures for big-endian O32. 2014-12-02 20:40:27 +00:00
MSP430
NVPTX [NVPTX] Do not emit .weak symbols for NVPTX 2014-12-01 21:16:17 +00:00
PowerPC [PowerPC] 'cc' should be an alias only to 'cr0' 2014-12-04 00:46:20 +00:00
R600 R600/SI: Remove i1 pseudo VALU ops 2014-12-03 05:22:35 +00:00
SPARC
SystemZ
Thumb This reverts commit r223306 and r223277. 2014-12-03 23:29:34 +00:00
Thumb2
X86 [X86] Improve a dag-combine that handles a vector extract -> zext sequence. 2014-12-04 13:49:51 +00:00
XCore