Reed Kotler 34ad085eec Add mips32 r1 to the list of supported targets for Mips fast-isel ... Summary: Expand list of supported targets for Mips to include mips32 r1. Previously it only include r2. More patches are coming where there is a difference but in the current patches as pushed upstream, r1 and r2 are equivalent. Test Plan: simplestorefp1.ll add new build bots at mips to test this flavor at both -O0 and -O2 Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D5306 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217821 91177308-0d34-0410-b5e6-96231b3b80d8		2014-09-15 20:30:25 +00:00
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AArch64	[FastISel][AArch64] Add support for non-native types for logical ops.	2014-09-13 23:46:28 +00:00
ARM	[ARM] Add Thumb-2 code size optimization regression test for LSR (register).	2014-09-11 10:45:50 +00:00
CPP
Generic
Hexagon
Inputs
Mips	Add mips32 r1 to the list of supported targets for Mips fast-isel	2014-09-15 20:30:25 +00:00
MSP430	Drop the W postfix on the 16-bit registers.	2014-09-10 06:58:14 +00:00
NVPTX
PowerPC	Fix a lot of confusion around inserting nops on empty functions.	2014-09-15 18:32:58 +00:00
R600	R600/SI: Prefer selecting more e64 instruction forms.	2014-09-15 17:15:02 +00:00
SPARC	Fix a lot of confusion around inserting nops on empty functions.	2014-09-15 18:32:58 +00:00
SystemZ
Thumb
Thumb2
X86	llvm/test/CodeGen/X86/peephole-fold-movsd.ll: Relax an expression for win32.	2014-09-15 19:00:31 +00:00
XCore