mirror of
https://github.com/c64scene-ar/llvm-6502.git
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3ddf868b04
Don't know why I didn't just do this in the first place. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206862 91177308-0d34-0410-b5e6-96231b3b80d8
382 lines
14 KiB
LLVM
382 lines
14 KiB
LLVM
; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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declare i32 @llvm.AMDGPU.imax(i32, i32) nounwind readnone
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; FUNC-LABEL: @sext_in_reg_i1_i32
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; SI: S_LOAD_DWORD [[ARG:s[0-9]+]],
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; SI: S_BFE_I32 [[SEXTRACT:s[0-9]+]], [[ARG]], 0x10000
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; SI: V_MOV_B32_e32 [[EXTRACT:v[0-9]+]], [[SEXTRACT]]
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; SI: BUFFER_STORE_DWORD [[EXTRACT]],
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; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+\.[XYZW]]], [[ADDR:T[0-9]+.[XYZW]]]
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; EG: BFE_INT [[RES]], {{.*}}, 0.0, 1
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; EG-NEXT: LSHR * [[ADDR]]
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define void @sext_in_reg_i1_i32(i32 addrspace(1)* %out, i32 %in) {
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%shl = shl i32 %in, 31
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%sext = ashr i32 %shl, 31
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store i32 %sext, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: @sext_in_reg_i8_to_i32
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; SI: S_ADD_I32 [[VAL:s[0-9]+]],
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; SI: S_SEXT_I32_I8 [[EXTRACT:s[0-9]+]], [[VAL]]
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; SI: V_MOV_B32_e32 [[VEXTRACT:v[0-9]+]], [[EXTRACT]]
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; SI: BUFFER_STORE_DWORD [[VEXTRACT]],
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; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+\.[XYZW]]], [[ADDR:T[0-9]+.[XYZW]]]
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; EG: ADD_INT
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; EG-NEXT: BFE_INT [[RES]], {{.*}}, 0.0, literal
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; EG-NEXT: LSHR * [[ADDR]]
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define void @sext_in_reg_i8_to_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
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%c = add i32 %a, %b ; add to prevent folding into extload
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%shl = shl i32 %c, 24
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%ashr = ashr i32 %shl, 24
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store i32 %ashr, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @sext_in_reg_i16_to_i32
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; SI: S_ADD_I32 [[VAL:s[0-9]+]],
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; SI: S_SEXT_I32_I16 [[EXTRACT:s[0-9]+]], [[VAL]]
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; SI: V_MOV_B32_e32 [[VEXTRACT:v[0-9]+]], [[EXTRACT]]
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; SI: BUFFER_STORE_DWORD [[VEXTRACT]],
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; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+\.[XYZW]]], [[ADDR:T[0-9]+.[XYZW]]]
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; EG: ADD_INT
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; EG-NEXT: BFE_INT [[RES]], {{.*}}, 0.0, literal
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; EG-NEXT: LSHR * [[ADDR]]
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define void @sext_in_reg_i16_to_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
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%c = add i32 %a, %b ; add to prevent folding into extload
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%shl = shl i32 %c, 16
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%ashr = ashr i32 %shl, 16
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store i32 %ashr, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @sext_in_reg_i8_to_v1i32
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; SI: S_ADD_I32 [[VAL:s[0-9]+]],
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; SI: S_SEXT_I32_I8 [[EXTRACT:s[0-9]+]], [[VAL]]
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; SI: V_MOV_B32_e32 [[VEXTRACT:v[0-9]+]], [[EXTRACT]]
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; SI: BUFFER_STORE_DWORD [[VEXTRACT]],
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; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+\.[XYZW]]], [[ADDR:T[0-9]+.[XYZW]]]
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; EG: ADD_INT
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; EG-NEXT: BFE_INT [[RES]], {{.*}}, 0.0, literal
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; EG-NEXT: LSHR * [[ADDR]]
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define void @sext_in_reg_i8_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i32> %a, <1 x i32> %b) nounwind {
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%c = add <1 x i32> %a, %b ; add to prevent folding into extload
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%shl = shl <1 x i32> %c, <i32 24>
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%ashr = ashr <1 x i32> %shl, <i32 24>
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store <1 x i32> %ashr, <1 x i32> addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @sext_in_reg_i1_to_i64
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; SI: S_ADD_I32 [[VAL:s[0-9]+]],
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; SI: S_BFE_I32 s{{[0-9]+}}, s{{[0-9]+}}, 0x10000
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; SI: S_MOV_B32 {{s[0-9]+}}, -1
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; SI: BUFFER_STORE_DWORDX2
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define void @sext_in_reg_i1_to_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
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%c = add i64 %a, %b
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%shl = shl i64 %c, 63
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%ashr = ashr i64 %shl, 63
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store i64 %ashr, i64 addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: @sext_in_reg_i8_to_i64
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; SI: S_ADD_I32 [[VAL:s[0-9]+]],
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; SI: S_SEXT_I32_I8 [[EXTRACT:s[0-9]+]], [[VAL]]
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; SI: S_MOV_B32 {{s[0-9]+}}, -1
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; SI: BUFFER_STORE_DWORDX2
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; EG: MEM_{{.*}} STORE_{{.*}} [[RES_LO:T[0-9]+\.[XYZW]]], [[ADDR_LO:T[0-9]+.[XYZW]]]
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; EG: MEM_{{.*}} STORE_{{.*}} [[RES_HI:T[0-9]+\.[XYZW]]], [[ADDR_HI:T[0-9]+.[XYZW]]]
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; EG: ADD_INT
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; EG-NEXT: BFE_INT {{\*?}} [[RES_LO]], {{.*}}, 0.0, literal
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; EG: ASHR [[RES_HI]]
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; EG-NOT: BFE_INT
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; EG: LSHR
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; EG: LSHR
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;; TODO Check address computation, using | with variables in {{}} does not work,
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;; also the _LO/_HI order might be different
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define void @sext_in_reg_i8_to_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
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%c = add i64 %a, %b
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%shl = shl i64 %c, 56
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%ashr = ashr i64 %shl, 56
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store i64 %ashr, i64 addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: @sext_in_reg_i16_to_i64
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; SI: S_ADD_I32 [[VAL:s[0-9]+]],
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; SI: S_SEXT_I32_I16 [[EXTRACT:s[0-9]+]], [[VAL]]
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; SI: S_MOV_B32 {{s[0-9]+}}, -1
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; SI: BUFFER_STORE_DWORDX2
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; EG: MEM_{{.*}} STORE_{{.*}} [[RES_LO:T[0-9]+\.[XYZW]]], [[ADDR_LO:T[0-9]+.[XYZW]]]
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; EG: MEM_{{.*}} STORE_{{.*}} [[RES_HI:T[0-9]+\.[XYZW]]], [[ADDR_HI:T[0-9]+.[XYZW]]]
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; EG: ADD_INT
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; EG-NEXT: BFE_INT {{\*?}} [[RES_LO]], {{.*}}, 0.0, literal
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; EG: ASHR [[RES_HI]]
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; EG-NOT: BFE_INT
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; EG: LSHR
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; EG: LSHR
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;; TODO Check address computation, using | with variables in {{}} does not work,
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;; also the _LO/_HI order might be different
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define void @sext_in_reg_i16_to_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
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%c = add i64 %a, %b
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%shl = shl i64 %c, 48
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%ashr = ashr i64 %shl, 48
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store i64 %ashr, i64 addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: @sext_in_reg_i32_to_i64
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; SI: S_LOAD_DWORD
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; SI: S_LOAD_DWORD
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; SI: S_ADD_I32 [[ADD:s[0-9]+]],
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; SI: S_ASHR_I32 s{{[0-9]+}}, [[ADD]], 31
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; SI: BUFFER_STORE_DWORDX2
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; EG: MEM_{{.*}} STORE_{{.*}} [[RES_LO:T[0-9]+\.[XYZW]]], [[ADDR_LO:T[0-9]+.[XYZW]]]
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; EG: MEM_{{.*}} STORE_{{.*}} [[RES_HI:T[0-9]+\.[XYZW]]], [[ADDR_HI:T[0-9]+.[XYZW]]]
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; EG-NOT: BFE_INT
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; EG: ADD_INT {{\*?}} [[RES_LO]]
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; EG: ASHR [[RES_HI]]
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; EG: ADD_INT
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; EG: LSHR
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; EG: LSHR
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;; TODO Check address computation, using | with variables in {{}} does not work,
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;; also the _LO/_HI order might be different
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define void @sext_in_reg_i32_to_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
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%c = add i64 %a, %b
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%shl = shl i64 %c, 32
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%ashr = ashr i64 %shl, 32
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store i64 %ashr, i64 addrspace(1)* %out, align 8
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ret void
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}
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; This is broken on Evergreen for some reason related to the <1 x i64> kernel arguments.
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; XFUNC-LABEL: @sext_in_reg_i8_to_v1i64
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; XSI: S_BFE_I32 [[EXTRACT:s[0-9]+]], {{s[0-9]+}}, 524288
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; XSI: S_ASHR_I32 {{v[0-9]+}}, [[EXTRACT]], 31
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; XSI: BUFFER_STORE_DWORD
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; XEG: BFE_INT
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; XEG: ASHR
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; define void @sext_in_reg_i8_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i64> %a, <1 x i64> %b) nounwind {
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; %c = add <1 x i64> %a, %b
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; %shl = shl <1 x i64> %c, <i64 56>
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; %ashr = ashr <1 x i64> %shl, <i64 56>
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; store <1 x i64> %ashr, <1 x i64> addrspace(1)* %out, align 8
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; ret void
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; }
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; FUNC-LABEL: @sext_in_reg_i1_in_i32_other_amount
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; SI-NOT: BFE
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; SI: S_LSHL_B32 [[REG:s[0-9]+]], {{s[0-9]+}}, 6
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; SI: S_ASHR_I32 {{s[0-9]+}}, [[REG]], 7
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; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+\.[XYZW]]], [[ADDR:T[0-9]+.[XYZW]]]
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; EG-NOT: BFE
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; EG: ADD_INT
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; EG: LSHL
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; EG: ASHR [[RES]]
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; EG: LSHR {{\*?}} [[ADDR]]
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define void @sext_in_reg_i1_in_i32_other_amount(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
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%c = add i32 %a, %b
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%x = shl i32 %c, 6
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%y = ashr i32 %x, 7
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store i32 %y, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: @sext_in_reg_v2i1_in_v2i32_other_amount
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; SI: S_LSHL_B32 [[REG0:s[0-9]+]], {{s[0-9]}}, 6
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; SI: S_ASHR_I32 {{s[0-9]+}}, [[REG0]], 7
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; SI: S_LSHL_B32 [[REG1:s[0-9]+]], {{s[0-9]}}, 6
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; SI: S_ASHR_I32 {{s[0-9]+}}, [[REG1]], 7
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; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+]]{{\.[XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]]
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; EG-NOT: BFE
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; EG: ADD_INT
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; EG: LSHL
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; EG: ASHR [[RES]]
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; EG: LSHL
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; EG: ASHR [[RES]]
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; EG: LSHR {{\*?}} [[ADDR]]
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define void @sext_in_reg_v2i1_in_v2i32_other_amount(<2 x i32> addrspace(1)* %out, <2 x i32> %a, <2 x i32> %b) nounwind {
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%c = add <2 x i32> %a, %b
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%x = shl <2 x i32> %c, <i32 6, i32 6>
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%y = ashr <2 x i32> %x, <i32 7, i32 7>
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store <2 x i32> %y, <2 x i32> addrspace(1)* %out, align 2
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ret void
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}
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; FUNC-LABEL: @sext_in_reg_v2i1_to_v2i32
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; SI: S_BFE_I32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000
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; SI: S_BFE_I32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000
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; SI: BUFFER_STORE_DWORDX2
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; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+]]{{\.[XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]]
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; EG: BFE_INT [[RES]]
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; EG: BFE_INT [[RES]]
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; EG: LSHR {{\*?}} [[ADDR]]
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define void @sext_in_reg_v2i1_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a, <2 x i32> %b) nounwind {
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%c = add <2 x i32> %a, %b ; add to prevent folding into extload
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%shl = shl <2 x i32> %c, <i32 31, i32 31>
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%ashr = ashr <2 x i32> %shl, <i32 31, i32 31>
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store <2 x i32> %ashr, <2 x i32> addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: @sext_in_reg_v4i1_to_v4i32
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; SI: S_BFE_I32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000
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; SI: S_BFE_I32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000
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; SI: S_BFE_I32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000
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; SI: S_BFE_I32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000
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; SI: BUFFER_STORE_DWORDX4
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; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+]]{{\.[XYZW][XYZW][XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]]
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; EG: BFE_INT [[RES]]
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; EG: BFE_INT [[RES]]
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; EG: BFE_INT [[RES]]
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; EG: BFE_INT [[RES]]
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; EG: LSHR {{\*?}} [[ADDR]]
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define void @sext_in_reg_v4i1_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> %b) nounwind {
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%c = add <4 x i32> %a, %b ; add to prevent folding into extload
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%shl = shl <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31>
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%ashr = ashr <4 x i32> %shl, <i32 31, i32 31, i32 31, i32 31>
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store <4 x i32> %ashr, <4 x i32> addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: @sext_in_reg_v2i8_to_v2i32
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; SI: S_SEXT_I32_I8 {{s[0-9]+}}, {{s[0-9]+}}
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; SI: S_SEXT_I32_I8 {{s[0-9]+}}, {{s[0-9]+}}
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; SI: BUFFER_STORE_DWORDX2
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; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+]]{{\.[XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]]
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; EG: BFE_INT [[RES]]
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; EG: BFE_INT [[RES]]
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; EG: LSHR {{\*?}} [[ADDR]]
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define void @sext_in_reg_v2i8_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a, <2 x i32> %b) nounwind {
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%c = add <2 x i32> %a, %b ; add to prevent folding into extload
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%shl = shl <2 x i32> %c, <i32 24, i32 24>
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%ashr = ashr <2 x i32> %shl, <i32 24, i32 24>
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store <2 x i32> %ashr, <2 x i32> addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: @sext_in_reg_v4i8_to_v4i32
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; SI: S_SEXT_I32_I8 {{s[0-9]+}}, {{s[0-9]+}}
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; SI: S_SEXT_I32_I8 {{s[0-9]+}}, {{s[0-9]+}}
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; SI: S_SEXT_I32_I8 {{s[0-9]+}}, {{s[0-9]+}}
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; SI: S_SEXT_I32_I8 {{s[0-9]+}}, {{s[0-9]+}}
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; SI: BUFFER_STORE_DWORDX4
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; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+]]{{\.[XYZW][XYZW][XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]]
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; EG: BFE_INT [[RES]]
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; EG: BFE_INT [[RES]]
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; EG: BFE_INT [[RES]]
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; EG: BFE_INT [[RES]]
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; EG: LSHR {{\*?}} [[ADDR]]
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define void @sext_in_reg_v4i8_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> %b) nounwind {
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%c = add <4 x i32> %a, %b ; add to prevent folding into extload
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%shl = shl <4 x i32> %c, <i32 24, i32 24, i32 24, i32 24>
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%ashr = ashr <4 x i32> %shl, <i32 24, i32 24, i32 24, i32 24>
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store <4 x i32> %ashr, <4 x i32> addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: @sext_in_reg_v2i16_to_v2i32
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; SI: S_SEXT_I32_I16 {{s[0-9]+}}, {{s[0-9]+}}
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; SI: S_SEXT_I32_I16 {{s[0-9]+}}, {{s[0-9]+}}
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; SI: BUFFER_STORE_DWORDX2
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; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+]]{{\.[XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]]
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; EG: BFE_INT [[RES]]
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; EG: BFE_INT [[RES]]
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; EG: LSHR {{\*?}} [[ADDR]]
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define void @sext_in_reg_v2i16_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a, <2 x i32> %b) nounwind {
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%c = add <2 x i32> %a, %b ; add to prevent folding into extload
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%shl = shl <2 x i32> %c, <i32 16, i32 16>
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%ashr = ashr <2 x i32> %shl, <i32 16, i32 16>
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store <2 x i32> %ashr, <2 x i32> addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: @testcase
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define void @testcase(i8 addrspace(1)* %out, i8 %a) nounwind {
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%and_a_1 = and i8 %a, 1
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%cmp_eq = icmp eq i8 %and_a_1, 0
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%cmp_slt = icmp slt i8 %a, 0
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%sel0 = select i1 %cmp_slt, i8 0, i8 %a
|
|
%sel1 = select i1 %cmp_eq, i8 0, i8 %a
|
|
%xor = xor i8 %sel0, %sel1
|
|
store i8 %xor, i8 addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
; FUNC-LABEL: @testcase_3
|
|
define void @testcase_3(i8 addrspace(1)* %out, i8 %a) nounwind {
|
|
%and_a_1 = and i8 %a, 1
|
|
%cmp_eq = icmp eq i8 %and_a_1, 0
|
|
%cmp_slt = icmp slt i8 %a, 0
|
|
%sel0 = select i1 %cmp_slt, i8 0, i8 %a
|
|
%sel1 = select i1 %cmp_eq, i8 0, i8 %a
|
|
%xor = xor i8 %sel0, %sel1
|
|
store i8 %xor, i8 addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
; FUNC-LABEL: @vgpr_sext_in_reg_v4i8_to_v4i32
|
|
; SI: V_BFE_I32 [[EXTRACT:v[0-9]+]], {{v[0-9]+}}, 0, 8
|
|
; SI: V_BFE_I32 [[EXTRACT:v[0-9]+]], {{v[0-9]+}}, 0, 8
|
|
; SI: V_BFE_I32 [[EXTRACT:v[0-9]+]], {{v[0-9]+}}, 0, 8
|
|
; SI: V_BFE_I32 [[EXTRACT:v[0-9]+]], {{v[0-9]+}}, 0, 8
|
|
define void @vgpr_sext_in_reg_v4i8_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %a, <4 x i32> addrspace(1)* %b) nounwind {
|
|
%loada = load <4 x i32> addrspace(1)* %a, align 16
|
|
%loadb = load <4 x i32> addrspace(1)* %b, align 16
|
|
%c = add <4 x i32> %loada, %loadb ; add to prevent folding into extload
|
|
%shl = shl <4 x i32> %c, <i32 24, i32 24, i32 24, i32 24>
|
|
%ashr = ashr <4 x i32> %shl, <i32 24, i32 24, i32 24, i32 24>
|
|
store <4 x i32> %ashr, <4 x i32> addrspace(1)* %out, align 8
|
|
ret void
|
|
}
|
|
|
|
; FUNC-LABEL: @vgpr_sext_in_reg_v4i16_to_v4i32
|
|
; SI: V_BFE_I32 [[EXTRACT:v[0-9]+]], {{v[0-9]+}}, 0, 16
|
|
; SI: V_BFE_I32 [[EXTRACT:v[0-9]+]], {{v[0-9]+}}, 0, 16
|
|
define void @vgpr_sext_in_reg_v4i16_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %a, <4 x i32> addrspace(1)* %b) nounwind {
|
|
%loada = load <4 x i32> addrspace(1)* %a, align 16
|
|
%loadb = load <4 x i32> addrspace(1)* %b, align 16
|
|
%c = add <4 x i32> %loada, %loadb ; add to prevent folding into extload
|
|
%shl = shl <4 x i32> %c, <i32 16, i32 16, i32 16, i32 16>
|
|
%ashr = ashr <4 x i32> %shl, <i32 16, i32 16, i32 16, i32 16>
|
|
store <4 x i32> %ashr, <4 x i32> addrspace(1)* %out, align 8
|
|
ret void
|
|
}
|
|
|
|
; FIXME: The BFE should really be eliminated. I think it should happen
|
|
; when computeMaskedBitsForTargetNode is implemented for imax.
|
|
|
|
; FUNC-LABEL: @sext_in_reg_to_illegal_type
|
|
; SI: BUFFER_LOAD_SBYTE
|
|
; SI: V_MAX_I32
|
|
; SI: V_BFE_I32
|
|
; SI: BUFFER_STORE_SHORT
|
|
define void @sext_in_reg_to_illegal_type(i16 addrspace(1)* nocapture %out, i8 addrspace(1)* nocapture %src) nounwind {
|
|
%tmp5 = load i8 addrspace(1)* %src, align 1
|
|
%tmp2 = sext i8 %tmp5 to i32
|
|
%tmp3 = tail call i32 @llvm.AMDGPU.imax(i32 %tmp2, i32 0) nounwind readnone
|
|
%tmp4 = trunc i32 %tmp3 to i8
|
|
%tmp6 = sext i8 %tmp4 to i16
|
|
store i16 %tmp6, i16 addrspace(1)* %out, align 2
|
|
ret void
|
|
}
|