llvm-6502/test/CodeGen/R600
Matt Arsenault 5049ca67c2 R600: Add mul24 intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208604 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 17:49:57 +00:00
..
32-bit-local-address-space.ll
64bit-kernel-args.ll
128bit-kernel-args.ll
add_i64.ll
add.ll
address-space.ll
and.ll
anyext.ll
array-ptr-calc-i32.ll
array-ptr-calc-i64.ll
atomic_load_add.ll
atomic_load_sub.ll
basic-branch.ll
basic-loop.ll
bfe_uint.ll
bfi_int.ll
big_alu.ll
bitcast.ll
build_vector.ll
call_fs.ll
call.ll
cayman-loop-bug.ll
cf_end.ll
cf-stack-bug.ll
codegen-prepare-addrmode-sext.ll
combine_vloads.ll
complex-folding.ll
dagcombiner-bug-illegal-vec4-int-to-fp.ll
disconnected-predset-break-bug.ll
dot4-folding.ll
elf.ll
elf.r600.ll
extload.ll
extract_vector_elt_i16.ll
fabs.ll R600/SI: Fold fabs/fneg into src input modifier 2014-05-10 19:18:39 +00:00
fadd64.ll
fadd.ll
fceil.ll
fcmp64.ll
fcmp-cnd.ll
fcmp-cnde-int-args.ll
fcmp.ll
fconst64.ll
fdiv64.ll
fdiv.ll
fetch-limits.r600.ll
fetch-limits.r700+.ll
ffloor.ll
floor.ll
fma.ll
fmad.ll
fmax.ll
fmin.ll
fmul64.ll
fmul.ll
fmuladd.ll
fneg-fabs.ll
fneg.ll R600/SI: Fold fabs/fneg into src input modifier 2014-05-10 19:18:39 +00:00
fp64_to_sint.ll
fp_to_sint.ll
fp_to_uint.ll
fpext.ll
fptrunc.ll
fsqrt.ll
fsub64.ll
fsub.ll
ftrunc.ll
gep-address-space.ll
gv-const-addrspace.ll
i8-to-double-to-float.ll
icmp64.ll
icmp-select-sete-reverse-args.ll
imm.ll
indirect-addressing-si.ll
indirect-private-64.ll
infinite-loop-evergreen.ll
infinite-loop.ll
insert_vector_elt_f64.ll
insert_vector_elt.ll
jump-address.ll
kcache-fold.ll
kernel-args.ll
lds-oqap-crash.ll
lds-output-queue.ll
lds-size.ll
legalizedag-bug-expand-setcc.ll
lit.local.cfg
literals.ll
llvm.AMDGPU.barrier.local.ll
llvm.AMDGPU.bfe.i32.ll
llvm.AMDGPU.bfe.u32.ll
llvm.AMDGPU.bfi.ll
llvm.AMDGPU.bfm.ll
llvm.AMDGPU.cube.ll
llvm.AMDGPU.imax.ll
llvm.AMDGPU.imin.ll
llvm.AMDGPU.imul24.ll R600: Add mul24 intrinsics 2014-05-12 17:49:57 +00:00
llvm.AMDGPU.kill.ll
llvm.AMDGPU.mul.ll
llvm.AMDGPU.tex.ll
llvm.AMDGPU.trunc.ll
llvm.AMDGPU.umax.ll
llvm.AMDGPU.umin.ll
llvm.AMDGPU.umul24.ll R600: Add mul24 intrinsics 2014-05-12 17:49:57 +00:00
llvm.cos.ll R600: Expand vector sin and cos. 2014-05-02 15:41:47 +00:00
llvm.exp2.ll
llvm.floor.ll
llvm.pow.ll
llvm.rint.f64.ll
llvm.rint.ll
llvm.round.ll
llvm.SI.fs.interp.constant.ll
llvm.SI.imageload.ll
llvm.SI.load.dword.ll
llvm.SI.resinfo.ll
llvm.SI.sample-masked.ll
llvm.SI.sample.ll
llvm.SI.sampled.ll
llvm.SI.sendmsg.ll
llvm.SI.tbuffer.store.ll
llvm.SI.tid.ll
llvm.sin.ll R600: Expand vector sin and cos. 2014-05-02 15:41:47 +00:00
llvm.sqrt.ll
llvm.trunc.ll
load64.ll
load-i1.ll
load-input-fold.ll
load.ll
load.vec.ll
local-64.ll
local-memory-two-objects.ll
local-memory.ll
loop-address.ll
loop-idiom.ll
lshl.ll
lshr.ll
mad_int24.ll
mad_uint24.ll
max-literals.ll
mubuf.ll
mul_int24.ll
mul_uint24.ll
mul.ll
mulhu.ll
or.ll
packetizer.ll
parallelandifcollapse.ll
parallelorifcollapse.ll
predicate-dp4.ll
predicates.ll
private-memory.ll
pv-packing.ll
pv.ll R600: Move MIN/MAX matching from LowerOperation() to PerformDAGCombine() 2014-05-09 16:42:16 +00:00
r600-encoding.ll
r600-export-fix.ll
r600-infinite-loop-bug-while-reorganizing-vector.ll
r600cfg.ll
README
reciprocal.ll
register-count-comments.ll
rotr.ll
rv7x0_count3.ll
salu-to-valu.ll R600/SI: Teach SIInstrInfo::moveToVALU() how to move S_LOAD_*_IMM instructions 2014-05-09 16:42:22 +00:00
schedule-fs-loop-nested-if.ll
schedule-fs-loop-nested.ll
schedule-fs-loop.ll
schedule-if-2.ll
schedule-if.ll
schedule-vs-if-nested-loop-failure.ll
schedule-vs-if-nested-loop.ll
sdiv.ll
select64.ll
select-vectors.ll
select.ll
selectcc-cnd.ll
selectcc-cnde-int.ll
selectcc-icmp-select-float.ll
selectcc-opt.ll
selectcc.ll R600: Expand i64 SELECT_CC 2014-05-09 16:42:19 +00:00
set-dx10.ll
setcc64.ll
setcc-equivalent.ll
setcc.ll
seto.ll R600/SI: Prettier display of input modifiers 2014-05-10 19:18:33 +00:00
setuo.ll R600/SI: Prettier display of input modifiers 2014-05-10 19:18:33 +00:00
sext-in-reg.ll
sgpr-control-flow.ll
sgpr-copy-duplicate-operand.ll
sgpr-copy.ll
shared-op-cycle.ll
shl.ll
si-annotate-cf-assertion.ll
si-lod-bias.ll
si-sgpr-spill.ll
si-vector-hang.ll
sign_extend.ll
simplify-demanded-bits-build-pair.ll Make SimplifyDemandedBits understand BUILD_PAIR 2014-05-12 17:14:48 +00:00
sint_to_fp64.ll
sint_to_fp.ll
smrd.ll R600/SI: Fix SMRD pattern for offsets > 32 bits 2014-05-09 16:42:21 +00:00
sra.ll
srl.ll
store-v3i32.ll
store-v3i64.ll
store-vector-ptrs.ll
store.ll R600: Expand TruncStore i64 -> {i16,i8} 2014-05-02 15:41:46 +00:00
store.r600.ll
structurize1.ll
structurize.ll
sub.ll R600: Expand i64 ISD:SUB 2014-05-05 21:47:15 +00:00
swizzle-export.ll
tex-clause-antidep.ll
texture-input-merge.ll
trunc-store-i1.ll
trunc-vector-store-assertion-failure.ll
trunc.ll
uaddo.ll
udiv.ll
udivrem64.ll
uint_to_fp.ll
unaligned-load-store.ll
unhandled-loop-condition-assertion.ll
unroll.ll
unsupported-cc.ll
urecip.ll
urem.ll
v1i64-kernel-arg.ll
v_cndmask.ll
valu-i1.ll
vertex-fetch-encoding.ll
vselect64.ll
vselect.ll
vtx-fetch-branch.ll
vtx-schedule.ll
wait.ll
work-item-intrinsics.ll
wrong-transalu-pos-fix.ll
xor.ll
zero_extend.ll

+==============================================================================+
| How to organize the lit tests                                                |
+==============================================================================+

- If you write a test for matching a single DAG opcode or intrinsic, it should
  go in a file called {opcode_name,intrinsic_name}.ll (e.g. fadd.ll)

- If you write a test that matches several DAG opcodes and checks for a single
  ISA instruction, then that test should go in a file called {ISA_name}.ll (e.g.
  bfi_int.ll

- For all other tests, use your best judgement for organizing tests and naming
  the files.

+==============================================================================+
| Naming conventions                                                           |
+==============================================================================+

- Use dash '-' and not underscore '_' to separate words in file names, unless
  the file is named after a DAG opcode or ISA instruction that has an
  underscore '_' in its name.