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https://github.com/c64scene-ar/llvm-6502.git
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358dec5180
- Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent. - Allow targets to specify alternative register allocation orders based on allocation hint. Part 2. - Use the register allocation hint system to implement more aggressive load / store multiple formation. - Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g. v1025 = LDR v1024, 0 v1026 = LDR v1024, 0 => v1025,v1026 = LDRD v1024, 0 If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair. - Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions. This is work in progress, not yet enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73381 91177308-0d34-0410-b5e6-96231b3b80d8 |
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| .. | ||
| DarwinTargetAsmInfo.h | ||
| ELFTargetAsmInfo.h | ||
| SubtargetFeature.h | ||
| Target.td | ||
| TargetAsmInfo.h | ||
| TargetCallingConv.td | ||
| TargetData.h | ||
| TargetELFWriterInfo.h | ||
| TargetFrameInfo.h | ||
| TargetInstrDesc.h | ||
| TargetInstrInfo.h | ||
| TargetInstrItineraries.h | ||
| TargetIntrinsicInfo.h | ||
| TargetJITInfo.h | ||
| TargetLowering.h | ||
| TargetMachine.h | ||
| TargetMachineRegistry.h | ||
| TargetMachOWriterInfo.h | ||
| TargetOptions.h | ||
| TargetRegisterInfo.h | ||
| TargetSchedule.td | ||
| TargetSelectionDAG.td | ||
| TargetSubtarget.h | ||