Matt Arsenault 35cc03a1ea R600/SI: Reimplement isLegalAddressingMode ...

Now that we sometimes know the address space, this can
theoretically do a better job.

This needs better test coverage, but this mostly depends on
first updating the loop optimizatiosn to provide the address
space.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239053 91177308-0d34-0410-b5e6-96231b3b80d8

2015-06-04 16:17:42 +00:00

..

AArch64

Don't create a MIN/MAX node if the underlying compare has more than one use.

2015-06-04 13:48:23 +00:00

ARM

ARM: Thumb2 LDRD/STRD supports independent input/output regs

2015-06-03 16:30:24 +00:00

BPF

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CPP

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Generic

Resubmit r237954 (MIR Serialization: print and parse LLVM IR using MIR format).

2015-05-27 18:02:19 +00:00

Hexagon

[Hexagon] Test doesn't work on all platforms. At any rate the uninitialized variable issue was fixed. Removing re-registering ASM backend.

2015-06-03 18:00:45 +00:00

Inputs

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Mips

[mips] Make TTypeEncoding indirect to allow .eh_frame to be read-only.

2015-06-02 20:32:50 +00:00

MIR

MIR Serialization: use correct line and column numbers for LLVM IR errors.

2015-05-29 17:05:41 +00:00

MSP430

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NVPTX

[NVPTXFavorNonGenericAddrSpaces] recursively trace into GEP and BitCast

2015-05-29 17:00:27 +00:00

PowerPC

Add support for VSX FMA single-precision instructions to the PPC back end

2015-05-29 17:13:25 +00:00

R600

R600/SI: Reimplement isLegalAddressingMode

2015-06-04 16:17:42 +00:00

SPARC

Add support for the Sparc implementation-defined "ASR" registers.

2015-05-18 16:29:48 +00:00

SystemZ

[DAGCombiner] Account for getVectorIdxTy() when narrowing vector load

2015-05-05 19:34:10 +00:00

Thumb

Thumb2: Modify codegen for memcpy intrinsic to prefer LDM/STM.

2015-05-28 20:02:45 +00:00

Thumb2

ARM: Thumb2 LDRD/STRD supports independent input/output regs

2015-06-03 16:30:24 +00:00

WinEH

[WinEH] C++ EH state numbering fixes

2015-05-20 23:22:24 +00:00

X86

Switch lowering: fix assert in buildBitTests (PR23738)

2015-06-04 15:55:00 +00:00

XCore

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