mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-26 23:29:22 +00:00
scheduling dependencies. Add assertion checks to help catch this. It appears the Mips target defaults to list-td, and it has a regression test that uses a physreg dependence. Such code was liable to be miscompiled, and now evokes an assertion failure. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62177 91177308-0d34-0410-b5e6-96231b3b80d8 |
||
---|---|---|
.. | ||
Alpha | ||
ARM | ||
CBackend | ||
CellSPU | ||
CPP | ||
Generic | ||
IA64 | ||
Mips | ||
PowerPC | ||
SPARC | ||
X86 | ||
XCore |