llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-10-02 17:55:18 +00:00

History

Stuart Hastings 3bf9125933 Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). This addresses a longstanding deficiency noted in many FIXMEs scattered across all the targets. This effectively moves the problem up one level, replacing eleven FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path through FastISel where we actually supply a DebugLoc, fixing Radar 7421831. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106243 91177308-0d34-0410-b5e6-96231b3b80d8		2010-06-17 22:43:56 +00:00
..
AsmPrinter
TargetInfo
Alpha.h
Alpha.td
AlphaBranchSelector.cpp
AlphaCallingConv.td
AlphaCodeEmitter.cpp
AlphaInstrFormats.td
AlphaInstrInfo.cpp	Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). This	2010-06-17 22:43:56 +00:00
AlphaInstrInfo.h	Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). This	2010-06-17 22:43:56 +00:00
AlphaInstrInfo.td	BR is a barrier.	2010-05-14 22:00:27 +00:00
AlphaISelDAGToDAG.cpp
AlphaISelLowering.cpp
AlphaISelLowering.h
AlphaJITInfo.cpp
AlphaJITInfo.h
AlphaLLRP.cpp
AlphaMachineFunctionInfo.h
AlphaMCAsmInfo.cpp
AlphaMCAsmInfo.h
AlphaRegisterInfo.cpp	cleanup	2010-06-02 13:53:17 +00:00
AlphaRegisterInfo.h	cleanup	2010-06-02 13:53:17 +00:00
AlphaRegisterInfo.td
AlphaRelocations.h
AlphaSchedule.td
AlphaSelectionDAGInfo.cpp	Implement a bunch more TargetSelectionDAGInfo infrastructure.	2010-05-11 17:31:57 +00:00
AlphaSelectionDAGInfo.h	Implement a bunch more TargetSelectionDAGInfo infrastructure.	2010-05-11 17:31:57 +00:00
AlphaSubtarget.cpp
AlphaSubtarget.h
AlphaTargetMachine.cpp	Implement a bunch more TargetSelectionDAGInfo infrastructure.	2010-05-11 17:31:57 +00:00
AlphaTargetMachine.h	Implement a bunch more TargetSelectionDAGInfo infrastructure.	2010-05-11 17:31:57 +00:00
CMakeLists.txt
Makefile
README.txt

README.txt

***

add gcc builtins for alpha instructions


***

custom expand byteswap into nifty 
extract/insert/mask byte/word/longword/quadword low/high
sequences

***

see if any of the extract/insert/mask operations can be added

***

match more interesting things for cmovlbc cmovlbs (move if low bit clear/set)

***

lower srem and urem

remq(i,j):  i - (j * divq(i,j)) if j != 0
remqu(i,j): i - (j * divqu(i,j)) if j != 0
reml(i,j):  i - (j * divl(i,j)) if j != 0
remlu(i,j): i - (j * divlu(i,j)) if j != 0

***

add crazy vector instructions (MVI):

(MIN|MAX)(U|S)(B8|W4) min and max, signed and unsigned, byte and word
PKWB, UNPKBW pack/unpack word to byte
PKLB UNPKBL pack/unpack long to byte
PERR pixel error (sum accross bytes of bytewise abs(i8v8 a - i8v8 b))

cmpbytes bytewise cmpeq of i8v8 a and i8v8 b (not part of MVI extentions)

this has some good examples for other operations that can be synthesised well 
from these rather meager vector ops (such as saturating add).
http://www.alphalinux.org/docs/MVI-full.html