Andrew Trick 667754e239 Remove code copied from GenRegisterInfo.inc. ... There's no apparent reason this code was copied from generated source into a .cpp. It sets a bad example for those working on other targets and trying to understand the register info API. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175849 91177308-0d34-0410-b5e6-96231b3b80d8		2013-02-22 01:15:08 +00:00
..
InstPrinter	Hexagon: Move HexagonMCInst.h to MCTargetDesc/HexagonMCInst.h.	2013-02-20 16:13:27 +00:00
MCTargetDesc	Hexagon: Move HexagonMCInst.h to MCTargetDesc/HexagonMCInst.h.	2013-02-20 16:13:27 +00:00
TargetInfo	Move all of the header files which are involved in modelling the LLVM IR	2013-01-02 11:36:10 +00:00
CMakeLists.txt	Extend Hexagon hardware loop generation to handle various additional cases:	2013-02-11 21:37:55 +00:00
Hexagon.h	Hexagon: Move HexagonMCInst.h to MCTargetDesc/HexagonMCInst.h.	2013-02-20 16:13:27 +00:00
Hexagon.td
HexagonAsmPrinter.cpp	Hexagon: Move HexagonMCInst.h to MCTargetDesc/HexagonMCInst.h.	2013-02-20 16:13:27 +00:00
HexagonAsmPrinter.h
HexagonCallingConv.td
HexagonCallingConvLower.cpp	Move all of the header files which are involved in modelling the LLVM IR	2013-01-02 11:36:10 +00:00
HexagonCallingConvLower.h
HexagonCFGOptimizer.cpp
HexagonExpandPredSpillCode.cpp
HexagonFixupHwLoops.cpp	Extend Hexagon hardware loop generation to handle various additional cases:	2013-02-11 21:37:55 +00:00
HexagonFrameLowering.cpp	Move the eliminateCallFramePseudoInstr method from TargetRegisterInfo	2013-02-21 20:05:00 +00:00
HexagonFrameLowering.h	Move the eliminateCallFramePseudoInstr method from TargetRegisterInfo	2013-02-21 20:05:00 +00:00
HexagonHardwareLoops.cpp	Extend Hexagon hardware loop generation to handle various additional cases:	2013-02-11 21:37:55 +00:00
HexagonInstrFormats.td	Hexagon: Change insn class to support instruction encoding.	2013-02-14 19:57:17 +00:00
HexagonInstrFormatsV4.td	Hexagon: Change insn class to support instruction encoding.	2013-02-14 19:57:17 +00:00
HexagonInstrInfo.cpp	Hexagon: add support for predicate-GPR copies.	2013-02-13 22:56:34 +00:00
HexagonInstrInfo.h	Implement HexagonInstrInfo::analyzeCompare.	2013-02-11 20:04:29 +00:00
HexagonInstrInfo.td	Hexagon: Change insn class to support instruction encoding.	2013-02-14 19:57:17 +00:00
HexagonInstrInfoV3.td
HexagonInstrInfoV4.td	Hexagon: Set appropriate TSFlags to the loads/stores with global address to	2013-02-15 17:52:07 +00:00
HexagonInstrInfoV5.td
HexagonIntrinsics.td
HexagonIntrinsicsDerived.td
HexagonIntrinsicsV3.td
HexagonIntrinsicsV4.td
HexagonIntrinsicsV5.td
HexagonISelDAGToDAG.cpp	Hexagon: Use absolute addressing mode loads/stores for global+offset	2013-02-13 21:38:46 +00:00
HexagonISelLowering.cpp	Hexagon: Expand cttz, ctlz, and ctpop for now.	2013-02-21 19:39:40 +00:00
HexagonISelLowering.h	Hexagon: Add V4 combine instructions and some more Def Pats for V2.	2013-02-04 15:52:56 +00:00
HexagonMachineFunctionInfo.h
HexagonMachineScheduler.cpp	MIsched: HazardRecognizers are created for each DAG. Free them.	2013-02-13 19:22:27 +00:00
HexagonMachineScheduler.h
HexagonMCInst.h
HexagonMCInstLower.cpp	Hexagon: Move HexagonMCInst.h to MCTargetDesc/HexagonMCInst.h.	2013-02-20 16:13:27 +00:00
HexagonNewValueJump.cpp
HexagonOperands.td
HexagonPeephole.cpp	Move all of the header files which are involved in modelling the LLVM IR	2013-01-02 11:36:10 +00:00
HexagonRegisterInfo.cpp	Remove code copied from GenRegisterInfo.inc.	2013-02-22 01:15:08 +00:00
HexagonRegisterInfo.h	Remove code copied from GenRegisterInfo.inc.	2013-02-22 01:15:08 +00:00
HexagonRegisterInfo.td
HexagonRemoveSZExtArgs.cpp	Move all of the header files which are involved in modelling the LLVM IR	2013-01-02 11:36:10 +00:00
HexagonSchedule.td	Hexagon: Change insn class to support instruction encoding.	2013-02-14 19:57:17 +00:00
HexagonScheduleV4.td	Hexagon: Change insn class to support instruction encoding.	2013-02-14 19:57:17 +00:00
HexagonSelectCCInfo.td
HexagonSelectionDAGInfo.cpp
HexagonSelectionDAGInfo.h
HexagonSplitTFRCondSets.cpp
HexagonSubtarget.cpp
HexagonSubtarget.h
HexagonTargetMachine.cpp	Hexagon: Use absolute addressing mode loads/stores for global+offset	2013-02-13 21:38:46 +00:00
HexagonTargetMachine.h	Switch TargetTransformInfo from an immutable analysis pass that requires	2013-01-07 01:37:14 +00:00
HexagonTargetObjectFile.cpp	Move all of the header files which are involved in modelling the LLVM IR	2013-01-02 11:36:10 +00:00
HexagonTargetObjectFile.h
HexagonVarargsCallingConvention.h
HexagonVLIWPacketizer.cpp	Hexagon: Use absolute addressing mode loads/stores for global+offset	2013-02-13 21:38:46 +00:00
LLVMBuild.txt
Makefile