Richard Sandiford 3ee0673e4f [SystemZ] Allow 8-bit operands to RISBG ... RISBG has three 8-bit operands (I3, I4 and I5). I'd originally restricted all three to 6 bits, since that's the only range we intended to use at the time. However, the top bit of I4 acts as a "zero" flag for RISBG, while the top bit of I3 acts as a "test" flag for RNSBG & co. This patch therefore allows them to have the full 8-bit range. I've left the fifth operand as a 6-bit value for now since the upper 2 bits have no defined meaning. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186070 91177308-0d34-0410-b5e6-96231b3b80d8		2013-07-11 08:37:13 +00:00
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AArch64
ARM	Add MC assembly/disassembly support for VRINT{A, N, P, M} to V8FP.	2013-07-09 11:26:18 +00:00
MBlaze
Mips	[mips] Increase the number of floating point control registers available to 32.	2013-07-01 20:31:44 +00:00
SystemZ	[SystemZ] Allow 8-bit operands to RISBG	2013-07-11 08:37:13 +00:00
X86	Update the X86 disassembler to use xacquire and xrelease when appropriate.	2013-06-20 22:32:18 +00:00
XCore