llvm-6502/lib/CodeGen/SelectionDAG
Nate Begeman 7042f15bde Teach the SelectionDAG how to transform select_cc eq, X, 0, 1, 0 into
either seteq X, 0 or srl (ctlz X), size(X-1), depending on what's legal
for the target.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22978 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-23 05:41:12 +00:00
..
LegalizeDAG.cpp Teach Legalize how to turn setcc into select_cc 2005-08-23 04:29:48 +00:00
Makefile
ScheduleDAG.cpp Add a fast-path for register values. Add support for constant pool entries, 2005-08-22 01:04:32 +00:00
SelectionDAG.cpp Teach the SelectionDAG how to transform select_cc eq, X, 0, 1, 0 into 2005-08-23 05:41:12 +00:00
SelectionDAGISel.cpp Fix a problem where constant expr shifts would not have their shift amount 2005-08-22 17:28:31 +00:00
SelectionDAGPrinter.cpp Print physreg register nodes with target names (e.g. F1) instead of numbers 2005-08-19 21:21:16 +00:00
TargetLowering.cpp For: memory operations -> stores 2005-07-19 04:52:44 +00:00