Evan Cheng 3ecadc816d Do not select tSXTB / tSXTH in thumb2 mode. ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76600 91177308-0d34-0410-b5e6-96231b3b80d8

2009-07-21 18:15:26 +00:00

..

Alpha

Make promotion in operation legalization for SETCC work correctly.

2009-07-17 05:16:04 +00:00

ARM

Fix ARM isle code that optimize multiply by constants which are power-of-2 +/- 1.

2009-07-21 00:31:12 +00:00

CBackend

Fix an erroneous check for isFNeg; the FNeg case is handled

2009-06-04 23:43:29 +00:00

CellSPU

Add some generic expansion logic for SMULO and UMULO. Fixes UMULO

2009-06-16 06:58:29 +00:00

CPP

Fix code emission for conditional branches.

2009-05-04 19:10:38 +00:00

Generic

remove tests for removed intrinsics.

2009-07-12 21:30:06 +00:00

IA64

…

Mips

Split the Add, Sub, and Mul instruction opcodes into separate

2009-06-04 22:49:04 +00:00

MSP430

Split the Add, Sub, and Mul instruction opcodes into separate

2009-06-04 22:49:04 +00:00

PIC16

add a testcase for the pic16 section handling stuff.

2009-07-21 16:48:20 +00:00

PowerPC

Teach MachineInstr::isRegTiedToDefOperand() to correctly parse inline asm operands.

2009-07-16 20:58:34 +00:00

SPARC

Split the Add, Sub, and Mul instruction opcodes into separate

2009-06-04 22:49:04 +00:00

SystemZ

convert this test to filecheck format, which is faster and avoids false matches of "st" -> "stdin"

2009-07-21 17:36:24 +00:00

Thumb

remove a very large testcase for now.

2009-07-21 06:28:36 +00:00

Thumb2

Do not select tSXTB / tSXTH in thumb2 mode.

2009-07-21 18:15:26 +00:00

X86

Another rewriter bug exposed by recent coalescer changes. ReuseInfo::GetRegForReload() should make sure the "switched" register is in the desired register class. I'm surprised this hasn't caused more failures in the past.

2009-07-21 09:15:00 +00:00

XCore

Combine an unaligned store of unaligned load into a memmove.

2009-07-16 12:50:48 +00:00