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42d9ca6299
In more detail, this patch adds the ability to parse, encode and decode MSA registers ($w0-$w31). The format of 2RF instructions (MipsMSAInstrFormat.td) was updated so that we could attach a test case to this patch i.e., the test case parses, encodes and decodes 2 MSA instructions. Following patches will add the remainder of the instructions. Note that DecodeMSA128BRegisterClass is missing from MipsDisassembler.td because it's not yet required at this stage and having it would cause a compiler warning (unused function). Patch by Matheus Almeida git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191412 91177308-0d34-0410-b5e6-96231b3b80d8 |
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| .. | ||
| msa | ||
| abicalls.ll | ||
| do_switch.ll | ||
| eh-frame.s | ||
| elf_basic.s | ||
| elf_eflags.ll | ||
| elf_st_other.ll | ||
| elf-bigendian.ll | ||
| elf-gprel-32-64.ll | ||
| elf-N64.ll | ||
| elf-objdump.s | ||
| elf-reginfo.ll | ||
| elf-relsym.ll | ||
| elf-tls.ll | ||
| expr1.s | ||
| higher_highest.ll | ||
| hilo-addressing.s | ||
| lea_64.ll | ||
| lit.local.cfg | ||
| micromips-alu-instructions.s | ||
| micromips-loadstore-instructions.s | ||
| micromips-loadstore-unaligned.s | ||
| micromips-movcond-instructions.s | ||
| micromips-multiply-instructions.s | ||
| micromips-shift-instructions.s | ||
| mips64-alu-instructions.s | ||
| mips64-instructions.s | ||
| mips64-register-names.s | ||
| mips64extins.ll | ||
| mips64shift.ll | ||
| mips_directives.s | ||
| mips_gprel16.ll | ||
| mips-alu-instructions.s | ||
| mips-control-instructions.s | ||
| mips-coprocessor-encodings.s | ||
| mips-dsp-instructions.s | ||
| mips-expansions.s | ||
| mips-fpu-instructions.s | ||
| mips-jump-instructions.s | ||
| mips-memory-instructions.s | ||
| mips-register-names.s | ||
| mips-relocations.s | ||
| multi-64bit-func.ll | ||
| nabi-regs.s | ||
| pr11877.s | ||
| r-mips-got-disp.ll | ||
| set-at-directive.s | ||
| sext_64_32.ll | ||
| sym-offset.ll | ||
| xgot.ll | ||