mirror of
https://github.com/c64scene-ar/llvm-6502.git
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439661395f
(including compilation, assembly). Move relocation model Reloc::Model from TargetMachine to MCCodeGenInfo so it's accessible even without TargetMachine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135468 91177308-0d34-0410-b5e6-96231b3b80d8
388 lines
13 KiB
C++
388 lines
13 KiB
C++
//===-- X86MCTargetDesc.cpp - X86 Target Descriptions -----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file provides X86 specific target descriptions.
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//
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//===----------------------------------------------------------------------===//
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#include "X86MCTargetDesc.h"
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#include "X86MCAsmInfo.h"
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#include "llvm/MC/MachineLocation.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Target/TargetRegistry.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/Support/Host.h"
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#define GET_REGINFO_MC_DESC
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#include "X86GenRegisterInfo.inc"
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#define GET_INSTRINFO_MC_DESC
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#include "X86GenInstrInfo.inc"
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#define GET_SUBTARGETINFO_MC_DESC
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#include "X86GenSubtargetInfo.inc"
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using namespace llvm;
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std::string X86_MC::ParseX86Triple(StringRef TT) {
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Triple TheTriple(TT);
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if (TheTriple.getArch() == Triple::x86_64)
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return "+64bit-mode";
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return "-64bit-mode";
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}
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/// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
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/// specified arguments. If we can't run cpuid on the host, return true.
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bool X86_MC::GetCpuIDAndInfo(unsigned value, unsigned *rEAX,
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unsigned *rEBX, unsigned *rECX, unsigned *rEDX) {
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#if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
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#if defined(__GNUC__)
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// gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
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asm ("movq\t%%rbx, %%rsi\n\t"
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"cpuid\n\t"
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"xchgq\t%%rbx, %%rsi\n\t"
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: "=a" (*rEAX),
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"=S" (*rEBX),
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"=c" (*rECX),
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"=d" (*rEDX)
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: "a" (value));
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return false;
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#elif defined(_MSC_VER)
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int registers[4];
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__cpuid(registers, value);
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*rEAX = registers[0];
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*rEBX = registers[1];
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*rECX = registers[2];
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*rEDX = registers[3];
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return false;
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#endif
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#elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
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#if defined(__GNUC__)
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asm ("movl\t%%ebx, %%esi\n\t"
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"cpuid\n\t"
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"xchgl\t%%ebx, %%esi\n\t"
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: "=a" (*rEAX),
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"=S" (*rEBX),
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"=c" (*rECX),
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"=d" (*rEDX)
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: "a" (value));
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return false;
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#elif defined(_MSC_VER)
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__asm {
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mov eax,value
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cpuid
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mov esi,rEAX
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mov dword ptr [esi],eax
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mov esi,rEBX
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mov dword ptr [esi],ebx
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mov esi,rECX
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mov dword ptr [esi],ecx
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mov esi,rEDX
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mov dword ptr [esi],edx
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}
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return false;
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#endif
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#endif
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return true;
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}
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void X86_MC::DetectFamilyModel(unsigned EAX, unsigned &Family,
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unsigned &Model) {
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Family = (EAX >> 8) & 0xf; // Bits 8 - 11
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Model = (EAX >> 4) & 0xf; // Bits 4 - 7
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if (Family == 6 || Family == 0xf) {
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if (Family == 0xf)
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// Examine extended family ID if family ID is F.
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Family += (EAX >> 20) & 0xff; // Bits 20 - 27
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// Examine extended model ID if family ID is 6 or F.
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Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
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}
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}
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unsigned X86_MC::getDwarfRegFlavour(StringRef TT, bool isEH) {
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Triple TheTriple(TT);
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if (TheTriple.getArch() == Triple::x86_64)
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return DWARFFlavour::X86_64;
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if (TheTriple.isOSDarwin())
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return isEH ? DWARFFlavour::X86_32_DarwinEH : DWARFFlavour::X86_32_Generic;
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if (TheTriple.getOS() == Triple::MinGW32 ||
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TheTriple.getOS() == Triple::Cygwin)
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// Unsupported by now, just quick fallback
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return DWARFFlavour::X86_32_Generic;
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return DWARFFlavour::X86_32_Generic;
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}
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/// getX86RegNum - This function maps LLVM register identifiers to their X86
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/// specific numbering, which is used in various places encoding instructions.
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unsigned X86_MC::getX86RegNum(unsigned RegNo) {
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switch(RegNo) {
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case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
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case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
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case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
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case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
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case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
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return N86::ESP;
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case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
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return N86::EBP;
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case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
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return N86::ESI;
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case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
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return N86::EDI;
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case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
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return N86::EAX;
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case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
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return N86::ECX;
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case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
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return N86::EDX;
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case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
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return N86::EBX;
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case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
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return N86::ESP;
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case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
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return N86::EBP;
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case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
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return N86::ESI;
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case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
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return N86::EDI;
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case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
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case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
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return RegNo-X86::ST0;
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case X86::XMM0: case X86::XMM8:
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case X86::YMM0: case X86::YMM8: case X86::MM0:
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return 0;
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case X86::XMM1: case X86::XMM9:
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case X86::YMM1: case X86::YMM9: case X86::MM1:
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return 1;
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case X86::XMM2: case X86::XMM10:
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case X86::YMM2: case X86::YMM10: case X86::MM2:
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return 2;
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case X86::XMM3: case X86::XMM11:
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case X86::YMM3: case X86::YMM11: case X86::MM3:
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return 3;
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case X86::XMM4: case X86::XMM12:
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case X86::YMM4: case X86::YMM12: case X86::MM4:
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return 4;
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case X86::XMM5: case X86::XMM13:
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case X86::YMM5: case X86::YMM13: case X86::MM5:
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return 5;
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case X86::XMM6: case X86::XMM14:
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case X86::YMM6: case X86::YMM14: case X86::MM6:
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return 6;
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case X86::XMM7: case X86::XMM15:
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case X86::YMM7: case X86::YMM15: case X86::MM7:
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return 7;
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case X86::ES: return 0;
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case X86::CS: return 1;
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case X86::SS: return 2;
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case X86::DS: return 3;
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case X86::FS: return 4;
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case X86::GS: return 5;
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case X86::CR0: case X86::CR8 : case X86::DR0: return 0;
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case X86::CR1: case X86::CR9 : case X86::DR1: return 1;
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case X86::CR2: case X86::CR10: case X86::DR2: return 2;
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case X86::CR3: case X86::CR11: case X86::DR3: return 3;
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case X86::CR4: case X86::CR12: case X86::DR4: return 4;
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case X86::CR5: case X86::CR13: case X86::DR5: return 5;
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case X86::CR6: case X86::CR14: case X86::DR6: return 6;
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case X86::CR7: case X86::CR15: case X86::DR7: return 7;
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// Pseudo index registers are equivalent to a "none"
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// scaled index (See Intel Manual 2A, table 2-3)
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case X86::EIZ:
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case X86::RIZ:
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return 4;
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default:
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assert((int(RegNo) > 0) && "Unknown physical register!");
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return 0;
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}
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}
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void X86_MC::InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI) {
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// FIXME: TableGen these.
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for (unsigned Reg = X86::NoRegister+1; Reg < X86::NUM_TARGET_REGS; ++Reg) {
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int SEH = X86_MC::getX86RegNum(Reg);
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switch (Reg) {
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case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
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case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
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case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
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case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
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case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
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case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
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case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
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case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
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case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
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case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
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case X86::YMM8: case X86::YMM9: case X86::YMM10: case X86::YMM11:
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case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15:
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SEH += 8;
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break;
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}
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MRI->mapLLVMRegToSEHReg(Reg, SEH);
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}
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}
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MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(StringRef TT, StringRef CPU,
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StringRef FS) {
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std::string ArchFS = X86_MC::ParseX86Triple(TT);
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if (!FS.empty()) {
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if (!ArchFS.empty())
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ArchFS = ArchFS + "," + FS.str();
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else
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ArchFS = FS;
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}
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std::string CPUName = CPU;
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if (CPUName.empty()) {
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#if defined (__x86_64__) || defined(__i386__)
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CPUName = sys::getHostCPUName();
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#else
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CPUName = "generic";
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#endif
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}
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MCSubtargetInfo *X = new MCSubtargetInfo();
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InitX86MCSubtargetInfo(X, TT, CPUName, ArchFS);
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return X;
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}
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// Force static initialization.
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extern "C" void LLVMInitializeX86MCSubtargetInfo() {
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TargetRegistry::RegisterMCSubtargetInfo(TheX86_32Target,
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X86_MC::createX86MCSubtargetInfo);
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TargetRegistry::RegisterMCSubtargetInfo(TheX86_64Target,
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X86_MC::createX86MCSubtargetInfo);
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}
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static MCInstrInfo *createX86MCInstrInfo() {
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MCInstrInfo *X = new MCInstrInfo();
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InitX86MCInstrInfo(X);
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return X;
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}
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extern "C" void LLVMInitializeX86MCInstrInfo() {
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TargetRegistry::RegisterMCInstrInfo(TheX86_32Target, createX86MCInstrInfo);
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TargetRegistry::RegisterMCInstrInfo(TheX86_64Target, createX86MCInstrInfo);
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}
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static MCRegisterInfo *createX86MCRegisterInfo(StringRef TT) {
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Triple TheTriple(TT);
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unsigned RA = (TheTriple.getArch() == Triple::x86_64)
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? X86::RIP // Should have dwarf #16.
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: X86::EIP; // Should have dwarf #8.
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MCRegisterInfo *X = new MCRegisterInfo();
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InitX86MCRegisterInfo(X, RA,
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X86_MC::getDwarfRegFlavour(TT, false),
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X86_MC::getDwarfRegFlavour(TT, true));
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X86_MC::InitLLVM2SEHRegisterMapping(X);
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return X;
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}
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extern "C" void LLVMInitializeX86MCRegisterInfo() {
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TargetRegistry::RegisterMCRegInfo(TheX86_32Target, createX86MCRegisterInfo);
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TargetRegistry::RegisterMCRegInfo(TheX86_64Target, createX86MCRegisterInfo);
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}
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static MCAsmInfo *createX86MCAsmInfo(const Target &T, StringRef TT) {
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Triple TheTriple(TT);
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bool is64Bit = TheTriple.getArch() == Triple::x86_64;
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MCAsmInfo *MAI;
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if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO) {
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if (is64Bit)
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MAI = new X86_64MCAsmInfoDarwin(TheTriple);
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else
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MAI = new X86MCAsmInfoDarwin(TheTriple);
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} else if (TheTriple.isOSWindows()) {
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MAI = new X86MCAsmInfoCOFF(TheTriple);
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} else {
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MAI = new X86ELFMCAsmInfo(TheTriple);
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}
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// Initialize initial frame state.
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// Calculate amount of bytes used for return address storing
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int stackGrowth = is64Bit ? -8 : -4;
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// Initial state of the frame pointer is esp+stackGrowth.
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MachineLocation Dst(MachineLocation::VirtualFP);
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MachineLocation Src(is64Bit ? X86::RSP : X86::ESP, stackGrowth);
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MAI->addInitialFrameState(0, Dst, Src);
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// Add return address to move list
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MachineLocation CSDst(is64Bit ? X86::RSP : X86::ESP, stackGrowth);
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MachineLocation CSSrc(is64Bit ? X86::RIP : X86::EIP);
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MAI->addInitialFrameState(0, CSDst, CSSrc);
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return MAI;
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}
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extern "C" void LLVMInitializeX86MCAsmInfo() {
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// Register the target asm info.
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RegisterMCAsmInfoFn A(TheX86_32Target, createX86MCAsmInfo);
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RegisterMCAsmInfoFn B(TheX86_64Target, createX86MCAsmInfo);
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}
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MCCodeGenInfo *createX86MCCodeGenInfo(StringRef TT, Reloc::Model RM) {
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MCCodeGenInfo *X = new MCCodeGenInfo();
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Triple T(TT);
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bool is64Bit = T.getArch() == Triple::x86_64;
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if (RM == Reloc::Default) {
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// Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
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// Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
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// use static relocation model by default.
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if (T.isOSDarwin()) {
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if (is64Bit)
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RM = Reloc::PIC_;
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else
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RM = Reloc::DynamicNoPIC;
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} else if (T.isOSWindows() && is64Bit)
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RM = Reloc::PIC_;
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else
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RM = Reloc::Static;
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}
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// ELF and X86-64 don't have a distinct DynamicNoPIC model. DynamicNoPIC
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// is defined as a model for code which may be used in static or dynamic
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// executables but not necessarily a shared library. On X86-32 we just
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// compile in -static mode, in x86-64 we use PIC.
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if (RM == Reloc::DynamicNoPIC) {
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if (is64Bit)
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RM = Reloc::PIC_;
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else if (!T.isOSDarwin())
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RM = Reloc::Static;
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}
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// If we are on Darwin, disallow static relocation model in X86-64 mode, since
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// the Mach-O file format doesn't support it.
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if (RM == Reloc::Static && T.isOSDarwin() && is64Bit)
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RM = Reloc::PIC_;
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X->InitMCCodeGenInfo(RM);
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return X;
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}
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extern "C" void LLVMInitializeX86MCCodeGenInfo() {
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// Register the target asm info.
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RegisterMCCodeGenInfoFn A(TheX86_32Target, createX86MCCodeGenInfo);
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RegisterMCCodeGenInfoFn B(TheX86_64Target, createX86MCCodeGenInfo);
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}
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