Jyotsna Verma a29a8965e2 Hexagon: Pass to replace tranfer/copy instructions into combine instruction ... where possible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181817 91177308-0d34-0410-b5e6-96231b3b80d8		2013-05-14 18:54:06 +00:00
..
absaddr-store.ll
absimm.ll	Hexagon: Remove duplicate instructions to handle global/immediate values	2013-04-23 17:11:46 +00:00
adde.ll
always-ext.ll	Hexagon: Use multiclass for combine and STri[bhwd]_shl_V4 instructions.	2013-04-23 21:17:40 +00:00
args.ll	Hexagon: Pass to replace tranfer/copy instructions into combine instruction	2013-05-14 18:54:06 +00:00
ashift-left-right.ll	Hexagon: Use multiclass for aslh, asrh, sxtb, sxth, zxtb and zxth.	2013-03-26 15:43:57 +00:00
block-addr.ll
BranchPredict.ll	Hexagon: Test case to check if branch probabilities are properly reflected in	2013-05-14 15:50:49 +00:00
cext-check.ll
cext-valid-packet1.ll
cext-valid-packet2.ll
cmp_pred2.ll	Hexagon: Remove assembler mapped instruction definitions.	2013-04-23 19:15:55 +00:00
cmp_pred_reg.ll
cmp_pred.ll
cmp-to-genreg.ll
cmp-to-predreg.ll
cmpb_pred.ll	TBAA: remove !tbaa from testing cases if not used.	2013-04-30 17:52:57 +00:00
combine_ir.ll	Hexagon - Add peephole optimizations for zero extends.	2013-05-02 20:22:51 +00:00
combine.ll
convertdptoint.ll
convertdptoll.ll
convertsptoint.ll
convertsptoll.ll
ctlz-cttz-ctpop.ll
dadd.ll
dmul.ll
double.ll
doubleconvert-ieee-rnd-near.ll
dsub.ll
dualstore.ll
extload-combine.ll	Hexagon: Add patterns to generate 'combine' instructions.	2013-05-14 17:16:38 +00:00
fadd.ll
fcmp.ll
float.ll
floatconvert-ieee-rnd-near.ll
fmul.ll
frame.ll
fsub.ll
fusedandshift.ll
gp-plus-offset-load.ll
gp-plus-offset-store.ll
gp-rel.ll	Hexagon: Use multiclass for gp-relative instructions.	2013-03-28 16:25:57 +00:00
hwloop-cleanup.ll
hwloop-const.ll	TBAA: remove !tbaa from testing cases if not used.	2013-04-30 17:52:57 +00:00
hwloop-dbg.ll	TBAA: remove !tbaa from testing cases if not used.	2013-04-30 17:52:57 +00:00
hwloop-le.ll
hwloop-lt1.ll
hwloop-lt.ll
hwloop-ne.ll
i1_VarArg.ll
i8_VarArg.ll
i16_VarArg.ll
idxload-with-zero-offset.ll
indirect-br.ll
lit.local.cfg
macint.ll
memops1.ll
memops2.ll	TBAA: remove !tbaa from testing cases if not used.	2013-04-30 17:52:57 +00:00
memops3.ll	TBAA: remove !tbaa from testing cases if not used.	2013-04-30 17:52:57 +00:00
memops.ll
misaligned-access.ll
mpy.ll
newvaluejump2.ll
newvaluejump.ll
newvaluestore.ll
opt-fabs.ll
opt-fneg.ll
packetize_cond_inst.ll	Hexagon: ArePredicatesComplement should not restrict itself to TFRs.	2013-05-14 16:36:34 +00:00
postinc-load.ll
postinc-store.ll
pred-absolute-store.ll
pred-gp.ll	Hexagon: Fix switch cases in HexagonVLIWPacketizer.cpp.	2013-05-10 20:27:34 +00:00
pred-instrs.ll	Hexagon: Use relation map for getMatchingCondBranchOpcode() and	2013-05-09 18:25:44 +00:00
predicate-copy.ll
remove_lsr.ll	TBAA: remove !tbaa from testing cases if not used.	2013-04-30 17:52:57 +00:00
simpletailcall.ll
split-const32-const64.ll	Hexagon: Fix Small Data support to handle -G 0 correctly.	2013-05-07 19:53:00 +00:00
static.ll
struct_args_large.ll
struct_args.ll
sube.ll
tfr-to-combine.ll	Hexagon: Pass to replace tranfer/copy instructions into combine instruction	2013-05-14 18:54:06 +00:00
union-1.ll	Hexagon - Add peephole optimizations for zero extends.	2013-05-02 20:22:51 +00:00
vaddh.ll	Enable all Hexagon tests.	2012-05-15 16:13:12 +00:00
validate-offset.ll
zextloadi1.ll