Chris Lattner 47cdf4abff Make the NDEBUG assertion stronger and more clear what is ... happening. Enhance scheduling to set the DEAD flag on implicit defs more aggressively. Before, we'd set an implicit def operand to dead if it were present in the SDNode corresponding to the machineinstr but had no use. Now we do it in this case AND if the implicit def does not exist in the SDNode at all. This exposes a couple of problems: one is the FIXME, which causes a live intervals crash on CodeGen/X86/sibcall.ll. The second is that it makes machinecse and licm more aggressive (which is a good thing) but also exposes a case where licm hoists a set0 and then it doesn't get resunk. Talking to codegen folks about both these issues, but I need this patch in in the meantime. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99485 91177308-0d34-0410-b5e6-96231b3b80d8		2010-03-25 05:40:48 +00:00
..
CallingConvLower.cpp
CMakeLists.txt
DAGCombiner.cpp	fix PR6533 by updating the br(xor) code to remember the case	2010-03-10 23:46:44 +00:00
FastISel.cpp	Remove dead include.	2010-03-11 02:28:48 +00:00
FunctionLoweringInfo.cpp	move target-independent opcodes out of TargetInstrInfo	2010-02-09 19:54:29 +00:00
FunctionLoweringInfo.h
InstrEmitter.cpp	Make the NDEBUG assertion stronger and more clear what is	2010-03-25 05:40:48 +00:00
InstrEmitter.h	reapply 99444/99445, which I speculatively reverted in	2010-03-25 04:41:16 +00:00
LegalizeDAG.cpp	Get rid of target-specific nodes for fp16 <-> fp32 conversion.	2010-03-18 22:35:37 +00:00
LegalizeFloatTypes.cpp	Turn calls to copysignl into an FCOPYSIGN node. Handle FCOPYSIGN nodes	2010-03-14 21:08:40 +00:00
LegalizeIntegerTypes.cpp	Revert 99335. getTypeToExpandTo's iterative behavior is actually	2010-03-23 22:44:42 +00:00
LegalizeTypes.cpp	Remove dead parameter passing.	2010-03-02 01:55:18 +00:00
LegalizeTypes.h	Turn calls to copysignl into an FCOPYSIGN node. Handle FCOPYSIGN nodes	2010-03-14 21:08:40 +00:00
LegalizeTypesGeneric.cpp	Add non-temporal flags and remove an assumption of default arguments.	2010-02-15 17:00:31 +00:00
LegalizeVectorOps.cpp	Revert an earlier change to SIGN_EXTEND_INREG for vectors. The VTSDNode	2010-01-09 02:13:55 +00:00
LegalizeVectorTypes.cpp	Fixed a widening bug where we were not using the correct size for the load	2010-03-19 01:19:52 +00:00
Makefile	make -fno-rtti the default unless a directory builds with REQUIRES_RTTI.	2010-01-24 20:43:08 +00:00
ScheduleDAGFast.cpp	Trim unneeded includes.	2010-01-21 21:44:43 +00:00
ScheduleDAGList.cpp
ScheduleDAGRRList.cpp	move target-independent opcodes out of TargetInstrInfo	2010-02-09 19:54:29 +00:00
ScheduleDAGSDNodes.cpp	Change how dbg_value sdnodes are converted into machine instructions. Their placement should be determined by the relative order of incoming llvm instructions. The scheduler will now use the SDNode ordering information to determine where to insert them. A dbg_value instruction is inserted after the instruction with the last highest source order and before the instruction with the next highest source order. It will optimize the placement by inserting right after the instruction that produces the value if they have consecutive order numbers.	2010-03-25 01:38:16 +00:00
ScheduleDAGSDNodes.h	Teach pre-regalloc scheduler to schedule loads from nearby addresses. It may improve cache locality. This is controlled by -cluster-loads for now.	2010-01-22 03:36:51 +00:00
SDNodeDbgValue.h	Change how dbg_value sdnodes are converted into machine instructions. Their placement should be determined by the relative order of incoming llvm instructions. The scheduler will now use the SDNode ordering information to determine where to insert them. A dbg_value instruction is inserted after the instruction with the last highest source order and before the instruction with the next highest source order. It will optimize the placement by inserting right after the instruction that produces the value if they have consecutive order numbers.	2010-03-25 01:38:16 +00:00
SDNodeOrdering.h
SelectionDAG.cpp	Change how dbg_value sdnodes are converted into machine instructions. Their placement should be determined by the relative order of incoming llvm instructions. The scheduler will now use the SDNode ordering information to determine where to insert them. A dbg_value instruction is inserted after the instruction with the last highest source order and before the instruction with the next highest source order. It will optimize the placement by inserting right after the instruction that produces the value if they have consecutive order numbers.	2010-03-25 01:38:16 +00:00
SelectionDAGBuilder.cpp	Change how dbg_value sdnodes are converted into machine instructions. Their placement should be determined by the relative order of incoming llvm instructions. The scheduler will now use the SDNode ordering information to determine where to insert them. A dbg_value instruction is inserted after the instruction with the last highest source order and before the instruction with the next highest source order. It will optimize the placement by inserting right after the instruction that produces the value if they have consecutive order numbers.	2010-03-25 01:38:16 +00:00
SelectionDAGBuilder.h	Assign the ordering of SDNodes in a much less intrusive fashion. After the	2010-01-28 21:51:40 +00:00
SelectionDAGISel.cpp	Emit dwarf variable info communicated by code generator through DBG_VALUE machine instructions.	2010-03-15 18:33:46 +00:00
SelectionDAGPrinter.cpp
TargetLowering.cpp	Remove the ConvertActions table and associated code, which is unused.	2010-03-24 00:53:38 +00:00