mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-22 10:29:35 +00:00
4a4d62bfb9
There were several overlapping problems here, and this solution is closely inspired by the one adopted in AArch64 in r201381. Firstly, scalarisation of v1i1 setcc operations simply fails if the input types are legal. This is fixed in LegalizeVectorTypes.cpp this time, and allows AArch64 code to be simplified slightly. Second, vselect with such a setcc feeding into it ends up in ScalarizeVectorOperand, where it's not handled. I experimented with an implementation, but found that whatever DAG came out was rather horrific. I think Hao's DAG combine approach is a good one for quality, though there are edge cases it won't catch (to be fixed separately). Should fix PR19335. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205625 91177308-0d34-0410-b5e6-96231b3b80d8 |
||
|---|---|---|
| .. | ||
| AArch64 | ||
| ARM | ||
| ARM64 | ||
| CPP | ||
| Generic | ||
| Hexagon | ||
| Inputs | ||
| Mips | ||
| MSP430 | ||
| NVPTX | ||
| PowerPC | ||
| R600 | ||
| SPARC | ||
| SystemZ | ||
| Thumb | ||
| Thumb2 | ||
| X86 | ||
| XCore | ||