llvm-6502/lib/CodeGen
Jakob Stoklund Olesen 4b76ffc1ff Revert "Remove references to INSERT_SUBREG after de-SSA" r107725.
Buildbot breakage.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107744 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 00:32:25 +00:00
..
AsmPrinter Propagate the AlignStack bit in InlineAsm's to the 2010-07-02 20:16:09 +00:00
PBQP
SelectionDAG By default, the eh.sjlj.setjmp/longjmp intrinsics should just do nothing rather 2010-07-06 23:44:52 +00:00
AggressiveAntiDepBreaker.cpp Make post-ra scheduling, anti-dep breaking, and register scavenger (conservatively) aware of predicated instructions. This enables ARM to move if-conversion before post-ra scheduler. 2010-06-16 07:35:02 +00:00
AggressiveAntiDepBreaker.h Make post-ra scheduling, anti-dep breaking, and register scavenger (conservatively) aware of predicated instructions. This enables ARM to move if-conversion before post-ra scheduler. 2010-06-16 07:35:02 +00:00
Analysis.cpp Move several SelectionDAG-independent utility functions out of the 2010-04-21 01:22:34 +00:00
AntiDepBreaker.h Make BreakAntiDependencies' SUnits argument const, and make the Begin 2010-04-19 23:11:58 +00:00
BranchFolding.cpp Tail merging pass shall not break up IT blocks. rdar://8115404 2010-06-22 01:18:16 +00:00
BranchFolding.h Tail merging pass shall not break up IT blocks. rdar://8115404 2010-06-22 01:18:16 +00:00
CalcSpillWeights.cpp Fix typo. 2010-07-03 01:09:18 +00:00
CMakeLists.txt Begin implementation of an inline spiller. 2010-06-29 23:58:39 +00:00
CodePlacementOpt.cpp Add some basic debug output. 2010-06-07 22:32:10 +00:00
CriticalAntiDepBreaker.cpp Make post-ra scheduling, anti-dep breaking, and register scavenger (conservatively) aware of predicated instructions. This enables ARM to move if-conversion before post-ra scheduler. 2010-06-16 07:35:02 +00:00
CriticalAntiDepBreaker.h Make post-ra scheduling, anti-dep breaking, and register scavenger (conservatively) aware of predicated instructions. This enables ARM to move if-conversion before post-ra scheduler. 2010-06-16 07:35:02 +00:00
DeadMachineInstructionElim.cpp Swap parameters of isSafeToMove and isSafeToReMat for consistency. 2010-03-02 19:03:01 +00:00
DwarfEHPrepare.cpp Use the catch-all selectors we already found when converting them to use the 2010-06-30 22:49:53 +00:00
ELF.h
ELFCodeEmitter.cpp getMachineBasicBlockAddress returns a uintptr_t - don't truncate 2010-06-29 13:34:20 +00:00
ELFCodeEmitter.h change EH related stuff (other than EH_LABEL) to use MCSymbol 2010-03-14 01:41:15 +00:00
ELFWriter.cpp Add more const qualifiers for LLVM IR pointers in CodeGen. 2010-04-15 04:33:49 +00:00
ELFWriter.h Add more const qualifiers for LLVM IR pointers in CodeGen. 2010-04-15 04:33:49 +00:00
GCMetadata.cpp switch GC_LABEL to use an MCSymbol operand instead of a label ID operand. 2010-03-14 07:27:07 +00:00
GCMetadataPrinter.cpp mcize the gc metadata printing stuff. 2010-04-04 07:39:04 +00:00
GCStrategy.cpp use ArgOperand API and CallSite to access arguments of CallInst 2010-06-25 08:48:19 +00:00
IfConversion.cpp Reapply my if-conversion cleanup from svn r106939 with fixes. 2010-06-29 00:55:23 +00:00
InlineSpiller.cpp Remove invalid assert 2010-07-02 19:54:47 +00:00
IntrinsicLowering.cpp use CallSite::arg_end instead of CallInst::op_end 2010-06-30 12:39:23 +00:00
LatencyPriorityQueue.cpp Use llvm::next' instead of next' to make VC++ 2010 happy. 2010-05-30 13:14:21 +00:00
LiveInterval.cpp Remove initialized but otherwise unused variables. 2010-06-29 11:22:26 +00:00
LiveIntervalAnalysis.cpp Revert "Remove references to INSERT_SUBREG after de-SSA" r107725. 2010-07-07 00:32:25 +00:00
LiveStackAnalysis.cpp VNInfos don't need to be destructed anymore. 2010-06-26 11:30:59 +00:00
LiveVariables.cpp fix a -Wbool-conversions warning from clang. 2010-06-14 18:28:34 +00:00
LLVMTargetMachine.cpp Temporarily disable on-demand fast-isel. 2010-07-01 12:15:30 +00:00
LowerSubregs.cpp Revert "Remove references to INSERT_SUBREG after de-SSA" r107725. 2010-07-07 00:32:25 +00:00
MachineBasicBlock.cpp Reapply r107655 with fixes; insert the pseudo instruction into 2010-07-06 20:24:04 +00:00
MachineCSE.cpp Detect and handle COPY in many places. 2010-07-03 00:04:37 +00:00
MachineDominators.cpp Don't bother calling releaseMemory before destroying the DominatorTreeBase. 2010-06-18 16:09:11 +00:00
MachineFunction.cpp Infer alignments of fixed frame objects when they are constructed. This ensures remat'ed loads from fixed slots have the right alignments. 2010-07-04 18:52:05 +00:00
MachineFunctionAnalysis.cpp Start function numbering at 0. 2010-04-17 16:29:15 +00:00
MachineFunctionPass.cpp Ok, third time's the charm. No changes from last time except the CMake 2010-04-02 23:17:14 +00:00
MachineFunctionPrinterPass.cpp Ok, third time's the charm. No changes from last time except the CMake 2010-04-02 23:17:14 +00:00
MachineInstr.cpp Print symbolic subreg indices on REG_SEQUENCE and INSERT_SUBREG. 2010-07-04 23:24:23 +00:00
MachineLICM.cpp Move PHIElimination's SplitCriticalEdge for MachineBasicBlocks out 2010-06-22 17:25:57 +00:00
MachineLoopInfo.cpp
MachineModuleInfo.cpp The JIT calls TidyLandingPads to tidy up the landing pads. However, because the 2010-04-16 08:46:10 +00:00
MachineModuleInfoImpls.cpp Add a bit along with the MCSymbols stored in the MachineModuleInfo maps that 2010-03-10 22:34:10 +00:00
MachinePassRegistry.cpp
MachineRegisterInfo.cpp Teach EmitLiveInCopies to omit copies for unused virtual registers, 2010-06-24 22:23:02 +00:00
MachineSink.cpp - Reapply r106066 now that the bzip2 build regression has been fixed. 2010-06-25 20:48:10 +00:00
MachineSSAUpdater.cpp Fix PR7096. When a block containing multiple defs is tail duplicated, the 2010-05-10 17:14:26 +00:00
MachineVerifier.cpp Allow ARM if-converter to be run after post allocation scheduling. 2010-06-18 23:09:54 +00:00
Makefile
ObjectCodeEmitter.cpp
OcamlGC.cpp
OptimizeExts.cpp It's an error to translate this: 2010-06-09 19:00:55 +00:00
OptimizePHIs.cpp Detect and handle COPY in many places. 2010-07-03 00:04:37 +00:00
Passes.cpp Use the fast register allocator by default for -O0 builds. 2010-06-03 00:39:06 +00:00
PHIElimination.cpp Move PHIElimination's SplitCriticalEdge for MachineBasicBlocks out 2010-06-22 17:25:57 +00:00
PHIElimination.h Move REG_SEQUENCE removal to 2addr pass. 2010-05-05 18:45:40 +00:00
PostRAHazardRecognizer.cpp Make post-ra scheduling, anti-dep breaking, and register scavenger (conservatively) aware of predicated instructions. This enables ARM to move if-conversion before post-ra scheduler. 2010-06-16 07:35:02 +00:00
PostRASchedulerList.cpp Allow ARM if-converter to be run after post allocation scheduling. 2010-06-18 23:09:54 +00:00
PreAllocSplitting.cpp Detect and handle COPY in many places. 2010-07-03 00:04:37 +00:00
ProcessImplicitDefs.cpp Revert "Remove references to INSERT_SUBREG after de-SSA" r107725. 2010-07-07 00:32:25 +00:00
PrologEpilogInserter.cpp Remove isSS argument from CreateFixedObject. Fixed objects cannot be spill slots so it's always false. 2010-07-03 00:40:23 +00:00
PrologEpilogInserter.h Clear up the last (famous last words) frame index value reuse issues for Thumb1. 2010-03-10 00:13:42 +00:00
PseudoSourceValue.cpp Fix memcheck-found leaks: one false positive from using new[], and one true 2010-03-04 22:15:01 +00:00
README.txt
RegAllocFast.cpp Detect and handle COPY in many places. 2010-07-03 00:04:37 +00:00
RegAllocLinearScan.cpp 80-col fixup. 2010-07-02 23:17:38 +00:00
RegAllocPBQP.cpp improve portability to systems that don't have powf/modf (e.g. solaris 9) 2010-05-15 17:10:24 +00:00
RegisterCoalescer.cpp Revert "Remove references to INSERT_SUBREG after de-SSA" r107725. 2010-07-07 00:32:25 +00:00
RegisterScavenging.cpp Make post-ra scheduling, anti-dep breaking, and register scavenger (conservatively) aware of predicated instructions. This enables ARM to move if-conversion before post-ra scheduler. 2010-06-16 07:35:02 +00:00
ScheduleDAG.cpp Remove trailing whitespace, no functionality changes. 2010-06-30 03:40:54 +00:00
ScheduleDAGEmit.cpp Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it 2010-05-06 20:33:48 +00:00
ScheduleDAGInstrs.cpp Fix the post-RA instruction scheduler to handle instructions referenced by 2010-05-19 22:57:06 +00:00
ScheduleDAGInstrs.h When processing loops for scheduling latencies (used for live outs on loop 2010-06-29 04:48:13 +00:00
ScheduleDAGPrinter.cpp
ShadowStackGC.cpp use ArgOperand API and CallSite to access arguments of CallInst 2010-06-25 08:48:19 +00:00
ShrinkWrapping.cpp
SimpleRegisterCoalescing.cpp Revert "Remove references to INSERT_SUBREG after de-SSA" r107725. 2010-07-07 00:32:25 +00:00
SimpleRegisterCoalescing.h Be more forgiving when calculating alias interference for physreg coalescing. 2010-07-06 20:31:51 +00:00
SjLjEHPrepare.cpp Handle array and vector typed parameters in sjljehprepare like we do 2010-06-30 22:20:38 +00:00
SlotIndexes.cpp Print the LSBs of a SlotIndex symbolically using letters referring to the 2010-06-24 17:31:07 +00:00
Spiller.cpp Fix to 80-col. 2010-07-06 18:35:20 +00:00
Spiller.h Add support for rematerialization to InlineSpiller. 2010-06-30 23:03:52 +00:00
StackProtector.cpp tighten up this code. 2010-07-06 15:59:27 +00:00
StackSlotColoring.cpp Revert "Remove references to INSERT_SUBREG after de-SSA" r107725. 2010-07-07 00:32:25 +00:00
StrongPHIElimination.cpp Don't track kills in VNInfo. Use interval ends instead. 2010-06-25 22:53:05 +00:00
TailDuplication.cpp Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it 2010-05-06 20:33:48 +00:00
TargetInstrInfoImpl.cpp Tail merging pass shall not break up IT blocks. rdar://8115404 2010-06-22 01:18:16 +00:00
TargetLoweringObjectFileImpl.cpp Fix a major regression on COFF targets introduced by r103267: 'discardable' section means that it is used only during the program load and can be discarded afterwards. 2010-07-06 15:24:56 +00:00
TwoAddressInstructionPass.cpp Revert "Remove references to INSERT_SUBREG after de-SSA" r107725. 2010-07-07 00:32:25 +00:00
UnreachableBlockElim.cpp revert r98550, it isn't necessary or sufficient. 2010-03-15 18:42:01 +00:00
VirtRegMap.cpp
VirtRegMap.h
VirtRegRewriter.cpp Cosmetic. 2010-06-25 17:41:07 +00:00
VirtRegRewriter.h Code clean up. Move includes from VirtRegRewriter.h to VirtRegRewriter.cpp. 2010-04-06 17:19:55 +00:00

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelyhood the store may become dead.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvments:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4

//===---------------------------------------------------------------------===//

The scheduler should be able to sort nearby instructions by their address. For
example, in an expanded memset sequence it's not uncommon to see code like this:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

Each of the stores is independent, and the scheduler is currently making an
arbitrary decision about the order.

//===---------------------------------------------------------------------===//

Another opportunitiy in this code is that the $0 could be moved to a register:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

This would save substantial code size, especially for longer sequences like
this. It would be easy to have a rule telling isel to avoid matching MOV32mi
if the immediate has more than some fixed number of uses. It's more involved
to teach the register allocator how to do late folding to recover from
excessive register pressure.