Tim Northover 4cc1407b84 ARM: Use ldrd/strd to spill 64-bit pairs when available. ...

This allows common sp-offsets to be part of the instruction and is
probably faster on modern CPUs too.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179977 91177308-0d34-0410-b5e6-96231b3b80d8

2013-04-21 11:57:07 +00:00

..

AArch64

Replace coff-/elf-dump with llvm-readobj

2013-04-12 04:06:46 +00:00

ARM

ARM: Use ldrd/strd to spill 64-bit pairs when available.

2013-04-21 11:57:07 +00:00

CPP

test commit: remove blank line.

2013-03-14 05:43:59 +00:00

Generic

XFAIL some of the generic CodeGen tests for Hexagon.

2013-03-25 21:04:16 +00:00

Hexagon

Hexagon: Enable SupportDebugInfomation and DwarfInSection flags.

2013-03-28 19:34:49 +00:00

Inputs

Revert "Adding DIImportedModules to DIScopes."

2013-03-28 02:44:59 +00:00

MBlaze

Remove unnecessary leading comment characters in lit-only file

2013-03-18 22:08:16 +00:00

Mips

[mips] Instruction selection patterns for DSP-ASE vector shifts.

2013-04-19 23:21:32 +00:00

MSP430

Remove unnecessary leading comment characters in lit-only file

2013-03-18 22:08:16 +00:00

NVPTX

[NVPTX] Remove support for SM < 2.0. This was never fully supported anyway.

2013-03-30 14:29:30 +00:00

PowerPC

Fix PPC optimizeCompareInstr swapped-sub argument handling

2013-04-19 22:08:38 +00:00

R600

R600: Add pattern for the BFI_INT instruction

2013-04-19 02:11:06 +00:00

SI

…

SPARC

Compile varargs functions for SPARCv9.

2013-04-20 22:49:16 +00:00

Thumb

Revert "Adding DIImportedModules to DIScopes."

2013-03-28 02:44:59 +00:00

Thumb2

SDAG: Handle scalarizing an extend of a <1 x iN> vector.

2013-03-07 05:47:54 +00:00

X86

Remove tbaa metadata.

2013-04-21 01:38:25 +00:00

XCore

[XCore] Extend test to check positve offsets are folded into addresses.

2013-04-16 20:05:52 +00:00