Ranjeet Singh 1666977cd0 [AArch64] AsmParser should be case insensitive about accepting vector register names. ...

Differential Revision: http://reviews.llvm.org/D10320


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239353 91177308-0d34-0410-b5e6-96231b3b80d8

2015-06-08 21:32:16 +00:00

..

AArch64

[AArch64] AsmParser should be case insensitive about accepting vector register names.

2015-06-08 21:32:16 +00:00

ARM

[ARM] Add support for -sp- FPUs and FPU none to TargetParser

2015-06-05 13:31:19 +00:00

AsmParser

Teaching llvm-mc how to understand the defsym command line option. This allows integer-constant symbols to be defined on the command line and used during assembly.

2015-06-07 01:46:24 +00:00

COFF

Revise test to run llc and llvm-mc separately.

2015-05-28 21:49:50 +00:00

Disassembler

ARM]: Add support for MMFR4_EL1 in assembler

2015-06-08 15:01:11 +00:00

ELF

Fix a regression in .pop_section.

2015-06-08 20:08:55 +00:00

Hexagon

[Hexagon] Reapply r239097 with tests corrected for shuffling and duplexing.

2015-06-05 16:00:11 +00:00

MachO

MC: Remove obsolete MachO UseAggressiveSymbolFolding.

2015-06-04 20:27:42 +00:00

Markup

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Mips

Revert "[mips] [IAS] Restore STI.FeatureBits in .set pop." (r239144).

2015-06-05 12:19:27 +00:00

PowerPC

Add testcase that would crash before the previous revert.

2015-06-04 05:51:13 +00:00

R600

R600/SI: Add assembler support for all CI and VI VOP2 instructions

2015-05-26 15:55:52 +00:00

Sparc

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SystemZ

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X86

AVX-512: Implemented 256/128bit VALIGND/Q instructions for SKX and KNL

2015-06-08 14:03:17 +00:00