llvm-6502/Hexagon at 4edd84da1b3f7fd73e96a13b6b7e183ad04ac7c4 - llvm-6502 - Applefritter: Git

6502/llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-22 13:29:44 +00:00

History

Andrew Trick 667754e239 Remove code copied from GenRegisterInfo.inc.

There's no apparent reason this code was copied from generated source
into a .cpp. It sets a bad example for those working on other targets
and trying to understand the register info API.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175849 91177308-0d34-0410-b5e6-96231b3b80d8

2013-02-22 01:15:08 +00:00

..

Hexagon: Move HexagonMCInst.h to MCTargetDesc/HexagonMCInst.h.

2013-02-20 16:13:27 +00:00

Hexagon: Move HexagonMCInst.h to MCTargetDesc/HexagonMCInst.h.

2013-02-20 16:13:27 +00:00

Move all of the header files which are involved in modelling the LLVM IR

2013-01-02 11:36:10 +00:00

CMakeLists.txt

Extend Hexagon hardware loop generation to handle various additional cases:

2013-02-11 21:37:55 +00:00

Hexagon.h

Hexagon: Move HexagonMCInst.h to MCTargetDesc/HexagonMCInst.h.

2013-02-20 16:13:27 +00:00

Hexagon.td

Move generic Hexagon subtarget information into Hexagon.td

2012-12-04 04:29:16 +00:00

HexagonAsmPrinter.cpp

Hexagon: Move HexagonMCInst.h to MCTargetDesc/HexagonMCInst.h.

2013-02-20 16:13:27 +00:00

HexagonAsmPrinter.h

Delete executive bit on ./lib/Target/Hexagon/HexagonAsmPrinter.h.

2012-12-29 15:23:06 +00:00

HexagonCallingConv.td

Hexagon V5 FP Support.

2012-05-10 20:20:25 +00:00

HexagonCallingConvLower.cpp

Move all of the header files which are involved in modelling the LLVM IR

2013-01-02 11:36:10 +00:00

HexagonCallingConvLower.h

Sort includes for all of the .h files under the 'lib' tree. These were

2012-12-04 07:12:27 +00:00

HexagonCFGOptimizer.cpp

Use the new script to sort the includes of every file under lib.

2012-12-03 16:50:05 +00:00

HexagonExpandPredSpillCode.cpp

Use the new script to sort the includes of every file under lib.

2012-12-03 16:50:05 +00:00

HexagonFixupHwLoops.cpp

Extend Hexagon hardware loop generation to handle various additional cases:

2013-02-11 21:37:55 +00:00

HexagonFrameLowering.cpp

Move the eliminateCallFramePseudoInstr method from TargetRegisterInfo

2013-02-21 20:05:00 +00:00

HexagonFrameLowering.h

Move the eliminateCallFramePseudoInstr method from TargetRegisterInfo

2013-02-21 20:05:00 +00:00

HexagonHardwareLoops.cpp

Extend Hexagon hardware loop generation to handle various additional cases:

2013-02-11 21:37:55 +00:00

HexagonInstrFormats.td

Hexagon: Change insn class to support instruction encoding.

2013-02-14 19:57:17 +00:00

HexagonInstrFormatsV4.td

Hexagon: Change insn class to support instruction encoding.

2013-02-14 19:57:17 +00:00

HexagonInstrInfo.cpp

Hexagon: add support for predicate-GPR copies.

2013-02-13 22:56:34 +00:00

HexagonInstrInfo.h

Implement HexagonInstrInfo::analyzeCompare.

2013-02-11 20:04:29 +00:00

HexagonInstrInfo.td

Hexagon: Change insn class to support instruction encoding.

2013-02-14 19:57:17 +00:00

HexagonInstrInfoV3.td

Remove variable_ops from call instructions in most targets.

2012-07-13 20:44:29 +00:00

HexagonInstrInfoV4.td

Hexagon: Set appropriate TSFlags to the loads/stores with global address to

2013-02-15 17:52:07 +00:00

HexagonInstrInfoV5.td

Revert 156634 upon request until code improvement changes are made.

2012-05-14 19:35:42 +00:00

HexagonIntrinsics.td

Hexagon V5 intrinsics support.

2012-05-11 19:39:13 +00:00

HexagonIntrinsicsDerived.td

Hexagon V5 intrinsics support.

2012-05-11 19:39:13 +00:00

HexagonIntrinsicsV3.td

…

HexagonIntrinsicsV4.td

…

HexagonIntrinsicsV5.td

Remove tabs.

2012-07-19 00:25:04 +00:00

HexagonISelDAGToDAG.cpp

Hexagon: Use absolute addressing mode loads/stores for global+offset

2013-02-13 21:38:46 +00:00

HexagonISelLowering.cpp

Hexagon: Expand cttz, ctlz, and ctpop for now.

2013-02-21 19:39:40 +00:00

HexagonISelLowering.h

Hexagon: Add V4 combine instructions and some more Def Pats for V2.

2013-02-04 15:52:56 +00:00

HexagonMachineFunctionInfo.h

…

HexagonMachineScheduler.cpp

MIsched: HazardRecognizers are created for each DAG. Free them.

2013-02-13 19:22:27 +00:00

HexagonMachineScheduler.h

Sort includes for all of the .h files under the 'lib' tree. These were

2012-12-04 07:12:27 +00:00

HexagonMCInst.h

Sort includes for all of the .h files under the 'lib' tree. These were

2012-12-04 07:12:27 +00:00

HexagonMCInstLower.cpp

Hexagon: Move HexagonMCInst.h to MCTargetDesc/HexagonMCInst.h.

2013-02-20 16:13:27 +00:00

HexagonNewValueJump.cpp

Use the new script to sort the includes of every file under lib.

2012-12-03 16:50:05 +00:00

HexagonOperands.td

Move all operand definitions into HexagonOperands.td

2012-12-04 05:00:31 +00:00

HexagonPeephole.cpp

Move all of the header files which are involved in modelling the LLVM IR

2013-01-02 11:36:10 +00:00

HexagonRegisterInfo.cpp

Remove code copied from GenRegisterInfo.inc.

2013-02-22 01:15:08 +00:00

HexagonRegisterInfo.h

Remove code copied from GenRegisterInfo.inc.

2013-02-22 01:15:08 +00:00

HexagonRegisterInfo.td

Hexagon V5 FP Support.

2012-05-10 20:20:25 +00:00

HexagonRemoveSZExtArgs.cpp

Move all of the header files which are involved in modelling the LLVM IR

2013-01-02 11:36:10 +00:00

HexagonSchedule.td

Hexagon: Change insn class to support instruction encoding.

2013-02-14 19:57:17 +00:00

HexagonScheduleV4.td

Hexagon: Change insn class to support instruction encoding.

2013-02-14 19:57:17 +00:00

HexagonSelectCCInfo.td

Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.

2012-02-18 12:03:15 +00:00

HexagonSelectionDAGInfo.cpp

…

HexagonSelectionDAGInfo.h

Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.

2012-02-18 12:03:15 +00:00

HexagonSplitTFRCondSets.cpp

Use the new script to sort the includes of every file under lib.

2012-12-03 16:50:05 +00:00

HexagonSubtarget.cpp

fix HexagonSubtarget parsing of -mv flag

2012-08-20 19:56:47 +00:00

HexagonSubtarget.h

Sort includes for all of the .h files under the 'lib' tree. These were

2012-12-04 07:12:27 +00:00

HexagonTargetMachine.cpp

Hexagon: Use absolute addressing mode loads/stores for global+offset

2013-02-13 21:38:46 +00:00

HexagonTargetMachine.h

Switch TargetTransformInfo from an immutable analysis pass that requires

2013-01-07 01:37:14 +00:00

HexagonTargetObjectFile.cpp

Move all of the header files which are involved in modelling the LLVM IR

2013-01-02 11:36:10 +00:00

HexagonTargetObjectFile.h

Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.

2012-02-18 12:03:15 +00:00

HexagonVarargsCallingConvention.h

Move TargetData to DataLayout.

2012-10-08 16:38:25 +00:00

HexagonVLIWPacketizer.cpp

Hexagon: Use absolute addressing mode loads/stores for global+offset

2013-02-13 21:38:46 +00:00

LLVMBuild.txt

Hexagon: enable assembler output through the MC layer.

2012-04-12 17:55:53 +00:00

Makefile

Hexagon: enable assembler output through the MC layer.

2012-04-12 17:55:53 +00:00