Chad Rosier 4fb3a966d0 [AArch64] Enable post-RA MI scheduler. ... Phabricator Revision: http://reviews.llvm.org/D5278 Patch by Sanjin Sijaric! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217693 91177308-0d34-0410-b5e6-96231b3b80d8		2014-09-12 17:40:39 +00:00
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AArch64	[AArch64] Enable post-RA MI scheduler.	2014-09-12 17:40:39 +00:00
ARM	[ARM] Add Thumb-2 code size optimization regression test for LSR (register).	2014-09-11 10:45:50 +00:00
CPP
Generic
Hexagon
Inputs
Mips
MSP430	Drop the W postfix on the 16-bit registers.	2014-09-10 06:58:14 +00:00
NVPTX
PowerPC	Address comments on r217622	2014-09-12 14:26:36 +00:00
R600	R600/SI: Fix off by 1 error in used register count	2014-09-11 22:51:37 +00:00
SPARC	Provide an implementation of getNoopForMachoTarget for SPARC.	2014-09-11 17:40:51 +00:00
SystemZ
Thumb
Thumb2
X86	llvm/test/CodeGen/X86/vec_ctbits.ll: Add explicit -mtriple=x86_64-unknown. It was incompatible to Win32 x64.	2014-09-12 15:10:56 +00:00
XCore