Colin LeMahieu 504c77f9c8 [Hexagon] Adding tstbit/bitclr/bitset instructions. ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224374 91177308-0d34-0410-b5e6-96231b3b80d8

2014-12-16 21:28:58 +00:00

..

AArch64

Update AArch64 ELF relocations to ABI 1.0

2014-11-26 10:49:18 +00:00

ARM

ARM: diagnose deprecated syntax

2014-12-16 05:53:25 +00:00

AsmParser

MC: AsmLexer: handle multi-character CommentStrings correctly

2014-08-14 02:51:43 +00:00

COFF

IR: Make metadata typeless in assembly

2014-12-15 19:07:53 +00:00

Disassembler

[Hexagon] Adding tstbit/bitclr/bitset instructions.

2014-12-16 21:28:58 +00:00

ELF

IR: Make metadata typeless in assembly

2014-12-15 19:07:53 +00:00

Hexagon

[Hexagon] Updating predicate register transfers and adding tstbit to allow select selection. Updating ll tests with predicate transfers that previously had nop encodings.

2014-12-09 18:16:49 +00:00

MachO

IR: Make metadata typeless in assembly

2014-12-15 19:07:53 +00:00

Markup

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Mips

[mips][microMIPS] Implement SWP and LWP instructions

2014-12-16 14:59:10 +00:00

PowerPC

[PowerPC] Add asm support for cache-inhibited ld/st instructions

2014-11-30 10:15:56 +00:00

R600

R600/SI: Start implementing an assembler

2014-11-14 14:08:00 +00:00

Sparc

Reduce verbiage of lit.local.cfg files

2014-06-09 22:42:55 +00:00

SystemZ

Exclude known and bugzilled failures from UBSan bootstrap

2014-09-17 20:17:52 +00:00

X86

[MC] Reset the MCInst in the matcher function before adding opcode/operands.

2014-12-16 18:05:28 +00:00