Jonathan Roelofs 506ed4d4a5 Lower thumbv4t & thumbv5 lo->lo copies through a push-pop sequence ... On pre-v6 hardware, 'MOV lo, lo' gives undefined results, so such copies need to be avoided. This patch trades simplicity for implementation time at the expense of performance... As they say: correctness first, then performance. See http://lists.cs.uiuc.edu/pipermail/llvmdev/2014-August/075998.html for a few ideas on how to make this better. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216138 91177308-0d34-0410-b5e6-96231b3b80d8		2014-08-20 23:38:50 +00:00
..
AArch64	[FastISel][AArch64] Don't fold the sign-/zero-extend from i1 into the compare.	2014-08-20 16:34:15 +00:00
ARM	Lower thumbv4t & thumbv5 lo->lo copies through a push-pop sequence	2014-08-20 23:38:50 +00:00
CPP
Generic	Use "weak alias" instead of "alias weak"	2014-07-30 22:51:54 +00:00
Hexagon	DebugInfo: Assert that any CU for which debug_loc lists are emitted, has at least one range.	2014-08-06 00:21:25 +00:00
Inputs
Mips	Fix fmul combines with constant splat vectors	2014-08-16 10:14:19 +00:00
MSP430
NVPTX	[NVPTX] Add some extra tests for mul.wide to test non-power-of-two source types	2014-07-23 20:23:49 +00:00
PowerPC	Reapply [FastISel] Let the target decide first if it wants to materialize a constant (215588).	2014-08-19 19:05:24 +00:00
R600	R600/SI: Move all fabs / fneg handling to patterns	2014-08-15 18:42:22 +00:00
SPARC
SystemZ
Thumb	Lower thumbv4t & thumbv5 lo->lo copies through a push-pop sequence	2014-08-20 23:38:50 +00:00
Thumb2	ARM: do not generate BLX instructions on Cortex-M CPUs.	2014-08-06 11:13:14 +00:00
X86	Don't prevent a vselect of constants from becoming a single load (PR20648).	2014-08-20 20:34:56 +00:00
XCore	llvm/test/CodeGen/XCore/dwarf_debug.ll: Fix not to be affected by *-win32.	2014-07-04 11:58:03 +00:00