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llvm-6502/lib/Target/R600
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Marek Olsak d922eb0be9 R600/SI: Fix MIN3/MAX3 on VI, define MED3 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227213 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-27 17:25:15 +00:00
..
AsmParser
R600/SI: Add a stub GCNTargetMachine
2015-01-06 18:00:21 +00:00
InstPrinter
[cleanup] Re-sort all the #include lines in LLVM using
2015-01-14 11:23:27 +00:00
MCTargetDesc
Add r224985 back with fixes.
2015-01-19 21:11:14 +00:00
TargetInfo
R600/SI: Add a stub GCNTargetMachine
2015-01-06 18:00:21 +00:00
AMDGPU.h
R600/SI: Use external symbols for scratch buffer
2015-01-20 17:49:47 +00:00
AMDGPU.td
R600/SI: Add subtarget feature to enable VGPR spilling for all shader types
2015-01-20 19:33:04 +00:00
AMDGPUAlwaysInlinePass.cpp
…
AMDGPUAsmPrinter.cpp
R600/SI: Emit .hsa.version section for amdhsa OS
2015-01-23 23:59:08 +00:00
AMDGPUAsmPrinter.h
std::unique_ptrify the MCStreamer argument to createAsmPrinter
2015-01-18 20:29:04 +00:00
AMDGPUCallingConv.td
…
AMDGPUFrameLowering.cpp
…
AMDGPUFrameLowering.h
…
AMDGPUInstrInfo.cpp
R600/SI: Don't shrink instructions whose e32 encoding doesn't exist
2015-01-15 18:42:51 +00:00
AMDGPUInstrInfo.h
R600/SI: Don't shrink instructions whose e32 encoding doesn't exist
2015-01-15 18:42:51 +00:00
AMDGPUInstrInfo.td
R600/SI: Add class intrinsic
2015-01-06 23:00:37 +00:00
AMDGPUInstructions.td
R600/SI: Add patterns for v_cvt_{flr|rpi}_i32_f32
2015-01-15 23:58:35 +00:00
AMDGPUIntrinsicInfo.cpp
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AMDGPUIntrinsicInfo.h
…
AMDGPUIntrinsics.td
…
AMDGPUISelDAGToDAG.cpp
R600/SI: Move i64 -> v2i32 load promotion into AMDGPUDAGToDAGISel::Select()
2015-01-23 22:05:45 +00:00
AMDGPUISelLowering.cpp
Move DataLayout back to the TargetMachine from TargetSubtargetInfo
2015-01-26 19:03:15 +00:00
AMDGPUISelLowering.h
R600: Try to use lower types for 64bit division if possible
2015-01-22 23:42:43 +00:00
AMDGPUMachineFunction.cpp
…
AMDGPUMachineFunction.h
…
AMDGPUMCInstLower.cpp
R600/SI: Use external symbols for scratch buffer
2015-01-20 17:49:47 +00:00
AMDGPUMCInstLower.h
R600/SI: Don't shrink instructions whose e32 encoding doesn't exist
2015-01-15 18:42:51 +00:00
AMDGPUPromoteAlloca.cpp
…
AMDGPURegisterInfo.cpp
…
AMDGPURegisterInfo.h
…
AMDGPURegisterInfo.td
…
AMDGPUSubtarget.cpp
Move DataLayout back to the TargetMachine from TargetSubtargetInfo
2015-01-26 19:03:15 +00:00
AMDGPUSubtarget.h
Move DataLayout back to the TargetMachine from TargetSubtargetInfo
2015-01-26 19:03:15 +00:00
AMDGPUTargetMachine.cpp
R600/SI: Spill VGPRs to scratch space for compute shaders
2015-01-14 15:42:31 +00:00
AMDGPUTargetMachine.h
Move DataLayout back to the TargetMachine from TargetSubtargetInfo
2015-01-26 19:03:15 +00:00
AMDGPUTargetTransformInfo.cpp
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AMDILCFGStructurizer.cpp
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AMDKernelCodeT.h
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CaymanInstructions.td
…
CIInstructions.td
R600/SI: Add VI instructions
2014-12-07 12:18:57 +00:00
CMakeLists.txt
R600/SI: Spill VGPRs to scratch space for compute shaders
2015-01-14 15:42:31 +00:00
EvergreenInstructions.td
R600/SI: Custom lower fround
2015-01-21 18:18:25 +00:00
LLVMBuild.txt
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Makefile
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Processors.td
R600/SI: Define a schedule model
2015-01-14 01:13:19 +00:00
R600ClauseMergePass.cpp
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R600ControlFlowFinalizer.cpp
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R600Defines.h
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R600EmitClauseMarkers.cpp
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R600ExpandSpecialInstrs.cpp
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R600InstrFormats.td
…
R600InstrInfo.cpp
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R600InstrInfo.h
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R600Instructions.td
R600/SI: Custom lower fround
2015-01-21 18:18:25 +00:00
R600Intrinsics.td
…
R600ISelLowering.cpp
[SelectionDAG] Allow targets to specify legality of extloads' result
2015-01-08 00:51:32 +00:00
R600ISelLowering.h
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R600MachineFunctionInfo.cpp
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R600MachineFunctionInfo.h
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R600MachineScheduler.cpp
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R600MachineScheduler.h
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R600OptimizeVectorRegisters.cpp
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R600Packetizer.cpp
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R600RegisterInfo.cpp
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R600RegisterInfo.h
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R600RegisterInfo.td
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R600Schedule.td
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R600TextureIntrinsicsReplacer.cpp
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R700Instructions.td
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SIAnnotateControlFlow.cpp
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SIDefines.h
R600/SI: Add subtarget feature to enable VGPR spilling for all shader types
2015-01-20 19:33:04 +00:00
SIFixSGPRCopies.cpp
R600/SI: Remove VReg_32 register class
2015-01-07 20:59:25 +00:00
SIFixSGPRLiveRanges.cpp
…
SIFoldOperands.cpp
R600/SI: Add pattern for bitcasting fp immediates to integers
2015-01-13 22:59:41 +00:00
SIInsertWaits.cpp
R600/SI: Insert s_waitcnt before s_barrier instructions.
2015-01-06 19:52:07 +00:00
SIInstrFormats.td
R600/SI: Add VI versions of LDS atomics
2015-01-27 17:25:07 +00:00
SIInstrInfo.cpp
R600/SI: Add subtarget feature to enable VGPR spilling for all shader types
2015-01-20 19:33:04 +00:00
SIInstrInfo.h
R600/SI: Don't shrink instructions whose e32 encoding doesn't exist
2015-01-15 18:42:51 +00:00
SIInstrInfo.td
R600/SI: Don't set patterns for chip-specific instructions while having pseudos
2015-01-27 17:25:11 +00:00
SIInstructions.td
R600/SI: Fix MIN3/MAX3 on VI, define MED3
2015-01-27 17:25:15 +00:00
SIIntrinsics.td
…
SIISelLowering.cpp
R600/SI: Add subtarget feature to enable VGPR spilling for all shader types
2015-01-20 19:33:04 +00:00
SIISelLowering.h
R600/SI: Fix bad code with unaligned byte vector loads
2015-01-14 01:35:22 +00:00
SILoadStoreOptimizer.cpp
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SILowerControlFlow.cpp
R600/SI: Add pattern for bitcasting fp immediates to integers
2015-01-13 22:59:41 +00:00
SILowerI1Copies.cpp
R600/SI: Remove VReg_32 register class
2015-01-07 20:59:25 +00:00
SIMachineFunctionInfo.cpp
R600/SI: Spill VGPRs to scratch space for compute shaders
2015-01-14 15:42:31 +00:00
SIMachineFunctionInfo.h
R600/SI: Add subtarget feature to enable VGPR spilling for all shader types
2015-01-20 19:33:04 +00:00
SIPrepareScratchRegs.cpp
R600/SI: Fix simple-loop.ll test
2015-01-20 19:33:02 +00:00
SIRegisterInfo.cpp
R600/SI: Add subtarget feature to enable VGPR spilling for all shader types
2015-01-20 19:33:04 +00:00
SIRegisterInfo.h
R600/SI: Use external symbols for scratch buffer
2015-01-20 17:49:47 +00:00
SIRegisterInfo.td
R600/SI: Use RegisterOperands to specify which operands can accept immediates
2015-01-12 19:33:18 +00:00
SISchedule.td
R600/SI: Define a schedule model
2015-01-14 01:13:19 +00:00
SIShrinkInstructions.cpp
R600/SI: Don't shrink instructions whose e32 encoding doesn't exist
2015-01-15 18:42:51 +00:00
SITypeRewriter.cpp
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VIInstrFormats.td
R600/SI: Add VI instructions
2014-12-07 12:18:57 +00:00
VIInstructions.td
R600/SI: Add VI versions of MUBUF loads and stores
2015-01-27 17:24:58 +00:00