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llvm-6502/lib/Target/Mips
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Akira Hatanaka 52b7321a48 [mips] Define instruction itineraries IIArith and IILogic. 
No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187468 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 00:55:34 +00:00
..
AsmParser
This patch implements parsing of mips FCC register operands. The example instructions have been added to test files.
2013-07-30 10:12:14 +00:00
Disassembler
[mips] Fix FP branch instructions to have explicit FP condition code register
2013-07-26 20:13:47 +00:00
InstPrinter
[mips] Define "bal" as a pseudo instruction. Also, fix bug in the InstAlias that
2013-07-30 20:24:24 +00:00
MCTargetDesc
Mips ELF: Mark object file as ABI compliant
2013-06-18 19:47:15 +00:00
TargetInfo
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CMakeLists.txt
Test commit to verify write access.
2013-07-16 17:44:23 +00:00
LLVMBuild.txt
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Makefile
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MicroMipsInstrFormats.td
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MicroMipsInstrInfo.td
[mips] Define instruction itineraries IIArith and IILogic.
2013-07-31 00:55:34 +00:00
Mips16FrameLowering.cpp
Use pointers to the MCAsmInfo and MCRegInfo.
2013-06-18 07:20:20 +00:00
Mips16FrameLowering.h
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Mips16HardFloat.cpp
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Mips16HardFloat.h
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Mips16InstrFormats.td
Mips td file formatting: white space and long lines
2013-05-16 20:08:49 +00:00
Mips16InstrInfo.cpp
Don't cache the instruction and register info from the TargetMachine, because
2013-06-07 07:04:14 +00:00
Mips16InstrInfo.h
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Mips16InstrInfo.td
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Mips16ISelDAGToDAG.cpp
Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change.
2013-06-19 21:36:55 +00:00
Mips16ISelDAGToDAG.h
Track IR ordering of SelectionDAG nodes 2/4.
2013-05-25 02:42:55 +00:00
Mips16ISelLowering.cpp
Mips: Remove global set.
2013-06-13 19:06:52 +00:00
Mips16ISelLowering.h
Mips: Remove global set.
2013-06-13 19:06:52 +00:00
Mips16RegisterInfo.cpp
Don't cache the instruction and register info from the TargetMachine, because
2013-06-07 07:04:14 +00:00
Mips16RegisterInfo.h
Don't cache the instruction and register info from the TargetMachine, because
2013-06-07 07:04:14 +00:00
Mips64InstrInfo.td
[mips] Define instruction itineraries IIArith and IILogic.
2013-07-31 00:55:34 +00:00
Mips.h
[mips] Add an IR transformation pass that optimizes calls to sqrt.
2013-06-11 22:21:44 +00:00
Mips.td
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MipsAnalyzeImmediate.cpp
Replace Count{Leading,Trailing}Zeros_{32,64} with count{Leading,Trailing}Zeros.
2013-05-24 22:23:49 +00:00
MipsAnalyzeImmediate.h
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MipsAsmPrinter.cpp
[mips] Do not emit ".option pic0" if target is mips64.
2013-06-26 19:08:49 +00:00
MipsAsmPrinter.h
DebugInfo: remove target-specific Frame Index handling for DBG_VALUE MachineInstrs
2013-06-16 20:34:27 +00:00
MipsCallingConv.td
Mips td file formatting: white space and long lines
2013-05-16 20:08:49 +00:00
MipsCodeEmitter.cpp
Don't cache the instruction and register info from the TargetMachine, because
2013-06-07 07:04:14 +00:00
MipsCondMov.td
[mips] Define instruction itineraries IIArith and IILogic.
2013-07-31 00:55:34 +00:00
MipsConstantIslandPass.cpp
Don't cache the instruction and register info from the TargetMachine, because
2013-06-07 07:04:14 +00:00
MipsDelaySlotFiller.cpp
Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid specifying the vector size.
2013-07-03 15:07:05 +00:00
MipsDSPInstrFormats.td
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MipsDSPInstrInfo.td
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MipsFrameLowering.cpp
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MipsFrameLowering.h
…
MipsInstrFormats.td
[mips] Delete instruction format for "bal".
2013-07-30 20:42:19 +00:00
MipsInstrFPU.td
This patch implements parsing of mips FCC register operands. The example instructions have been added to test files.
2013-07-30 10:12:14 +00:00
MipsInstrInfo.cpp
DebugInfo: remove target-specific Frame Index handling for DBG_VALUE MachineInstrs
2013-06-16 20:34:27 +00:00
MipsInstrInfo.h
DebugInfo: remove target-specific Frame Index handling for DBG_VALUE MachineInstrs
2013-06-16 20:34:27 +00:00
MipsInstrInfo.td
[mips] Define instruction itineraries IIArith and IILogic.
2013-07-31 00:55:34 +00:00
MipsISelDAGToDAG.cpp
Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change.
2013-06-19 21:36:55 +00:00
MipsISelDAGToDAG.h
…
MipsISelLowering.cpp
[mips] Implement llvm.trap intrinsic.
2013-07-26 20:58:55 +00:00
MipsISelLowering.h
Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector size.
2013-07-14 04:42:23 +00:00
MipsJITInfo.cpp
[test commit] Minor comment change.
2013-07-24 13:02:35 +00:00
MipsJITInfo.h
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MipsLongBranch.cpp
Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid specifying the vector size.
2013-07-04 01:31:24 +00:00
MipsMachineFunction.cpp
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MipsMachineFunction.h
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MipsMCInstLower.cpp
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MipsMCInstLower.h
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MipsModuleISelDAGToDAG.cpp
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MipsModuleISelDAGToDAG.h
…
MipsOptimizeMathLibCalls.cpp
[mips] Add an IR transformation pass that optimizes calls to sqrt.
2013-06-11 22:21:44 +00:00
MipsOs16.cpp
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MipsOs16.h
…
MipsRegisterInfo.cpp
…
MipsRegisterInfo.h
…
MipsRegisterInfo.td
This patch implements parsing of mips FCC register operands. The example instructions have been added to test files.
2013-07-30 10:12:14 +00:00
MipsRelocations.h
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MipsSchedule.td
[mips] Define instruction itineraries IIArith and IILogic.
2013-07-31 00:55:34 +00:00
MipsSEFrameLowering.cpp
Use pointers to the MCAsmInfo and MCRegInfo.
2013-06-18 07:20:20 +00:00
MipsSEFrameLowering.h
…
MipsSEInstrInfo.cpp
[mips] Use ADDu instead of OR to copy general purpose registers. Also, delete
2013-07-22 18:52:22 +00:00
MipsSEInstrInfo.h
[mips] Use function TargetInstrInfo::getRegClass.
2013-06-11 18:48:16 +00:00
MipsSEISelDAGToDAG.cpp
Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change.
2013-06-19 21:36:55 +00:00
MipsSEISelDAGToDAG.h
Track IR ordering of SelectionDAG nodes 2/4.
2013-05-25 02:42:55 +00:00
MipsSEISelLowering.cpp
[mips] Improve code generation for constant multiplication using shifts, adds and
2013-06-26 18:48:17 +00:00
MipsSEISelLowering.h
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MipsSelectionDAGInfo.cpp
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MipsSelectionDAGInfo.h
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MipsSERegisterInfo.cpp
Don't cache the instruction and register info from the TargetMachine, because
2013-06-07 07:04:14 +00:00
MipsSERegisterInfo.h
Don't cache the instruction and register info from the TargetMachine, because
2013-06-07 07:04:14 +00:00
MipsSubtarget.cpp
…
MipsSubtarget.h
[mips] Implement MipsTargetMachine::getInstrItineraryData().
2013-07-12 23:33:22 +00:00
MipsTargetMachine.cpp
[mips] Implement MipsTargetMachine::getInstrItineraryData().
2013-07-12 23:33:22 +00:00
MipsTargetMachine.h
[mips] Implement MipsTargetMachine::getInstrItineraryData().
2013-07-12 23:33:22 +00:00
MipsTargetObjectFile.cpp
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MipsTargetObjectFile.h
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