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https://github.com/c64scene-ar/llvm-6502.git
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44efa200e2
Minor patch to fix an issue in XFormVExtractWithShuffleIntoLoad where a load is unary shuffled, then bitcast (to a type with the same number of elements) before extracting an element. An undef was created for the second shuffle operand using the original (post-bitcasted) vector type instead of the pre-bitcasted type like the rest of the shuffle node - this was then causing an assertion on the different types later on inside SelectionDAG::getVectorShuffle. Differential Revision: http://reviews.llvm.org/D5917 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220592 91177308-0d34-0410-b5e6-96231b3b80d8
65 lines
2.1 KiB
LLVM
65 lines
2.1 KiB
LLVM
; RUN: llc < %s -march=x86 -mattr=+sse2 -mcpu=yonah | FileCheck %s
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; RUN: llc < %s -march=x86-64 -mattr=+sse2 -mcpu=core2 | FileCheck %s
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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define i32 @t(<2 x i64>* %val) nounwind {
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; CHECK-LABEL: t:
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; CHECK-NOT: movd
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; CHECK: movl 8(
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; CHECK-NEXT: ret
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%tmp2 = load <2 x i64>* %val, align 16 ; <<2 x i64>> [#uses=1]
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%tmp3 = bitcast <2 x i64> %tmp2 to <4 x i32> ; <<4 x i32>> [#uses=1]
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%tmp4 = extractelement <4 x i32> %tmp3, i32 2 ; <i32> [#uses=1]
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ret i32 %tmp4
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}
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; Case where extractelement of load ends up as undef.
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; (Making sure this doesn't crash.)
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define i32 @t2(<8 x i32>* %xp) {
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; CHECK-LABEL: t2:
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; CHECK: ret
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%x = load <8 x i32>* %xp
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%Shuff68 = shufflevector <8 x i32> %x, <8 x i32> undef, <8 x i32> <i32
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undef, i32 7, i32 9, i32 undef, i32 13, i32 15, i32 1, i32 3>
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%y = extractelement <8 x i32> %Shuff68, i32 0
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ret i32 %y
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}
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; This case could easily end up inf-looping in the DAG combiner due to an
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; low alignment load of the vector which prevents us from reliably forming a
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; narrow load.
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; FIXME: It would be nice to detect whether the target has fast and legal
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; unaligned loads and use them here.
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define void @t3() {
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; CHECK-LABEL: t3:
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;
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; This movs the entire vector, shuffling the high double down. If we fixed the
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; FIXME above it would just move the high double directly.
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; CHECK: movupd
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; CHECK: shufpd
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; CHECK: movlpd
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bb:
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%tmp13 = load <2 x double>* undef, align 1
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%.sroa.3.24.vec.extract = extractelement <2 x double> %tmp13, i32 1
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store double %.sroa.3.24.vec.extract, double* undef, align 8
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unreachable
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}
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; Case where a load is unary shuffled, then bitcast (to a type with the same
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; number of elements) before extractelement.
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; This is testing for an assertion - the extraction was assuming that the undef
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; second shuffle operand was a post-bitcast type instead of a pre-bitcast type.
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define i64 @t4(<2 x double>* %a) {
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; CHECK-LABEL: t4:
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; CHECK: mov
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; CHECK: ret
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%b = load <2 x double>* %a, align 16
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%c = shufflevector <2 x double> %b, <2 x double> %b, <2 x i32> <i32 1, i32 0>
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%d = bitcast <2 x double> %c to <2 x i64>
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%e = extractelement <2 x i64> %d, i32 1
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ret i64 %e
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}
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