Bob Wilson 5afffaed5c Handle ARM inline asm "w" constraints with 64-bit ("d") registers. ... The change in SelectionDAGBuilder is needed to allow using bitcasts to convert between f64 (the default type for ARM "d" registers) and 64-bit Neon vector types. Radar 7457110. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91649 91177308-0d34-0410-b5e6-96231b3b80d8		2009-12-18 01:03:29 +00:00
..
CallingConvLower.cpp
CMakeLists.txt
DAGCombiner.cpp	Revert this dag combine change:	2009-12-17 00:40:05 +00:00
FastISel.cpp
FunctionLoweringInfo.cpp
FunctionLoweringInfo.h
InstrEmitter.cpp
InstrEmitter.h
LegalizeDAG.cpp	Introduce EVT::getHalfSizedIntegerVT() for use in ExpandUnalignedStore() in	2009-12-17 20:09:43 +00:00
LegalizeFloatTypes.cpp
LegalizeIntegerTypes.cpp
LegalizeTypes.cpp
LegalizeTypes.h	Implement vector widening, splitting, and scalarizing for SIGN_EXTEND_INREG.	2009-12-11 21:31:27 +00:00
LegalizeTypesGeneric.cpp
LegalizeVectorOps.cpp	Implement vector widening, splitting, and scalarizing for SIGN_EXTEND_INREG.	2009-12-11 21:31:27 +00:00
LegalizeVectorTypes.cpp	Implement vector widening, splitting, and scalarizing for SIGN_EXTEND_INREG.	2009-12-11 21:31:27 +00:00
Makefile
ScheduleDAGFast.cpp
ScheduleDAGList.cpp
ScheduleDAGRRList.cpp
ScheduleDAGSDNodes.cpp	Reapply r91392, it was only unmasking the bug, and since TOT is still broken having it reverted does no good.	2009-12-16 20:10:05 +00:00
ScheduleDAGSDNodes.h
SelectionDAG.cpp	Reapply r91392, it was only unmasking the bug, and since TOT is still broken having it reverted does no good.	2009-12-16 20:10:05 +00:00
SelectionDAGBuilder.cpp	Handle ARM inline asm "w" constraints with 64-bit ("d") registers.	2009-12-18 01:03:29 +00:00
SelectionDAGBuilder.h
SelectionDAGISel.cpp	Fix this to properly clear the FastISel debug location. Thanks to	2009-12-14 23:08:09 +00:00
SelectionDAGPrinter.cpp
TargetLowering.cpp	Implement vector widening, splitting, and scalarizing for SIGN_EXTEND_INREG.	2009-12-11 21:31:27 +00:00