Arnold Schwaighofer d42730dc71 IfConverter: Use TargetSchedule for instruction latencies ... For targets that have instruction itineraries this means no change. Targets that move over to the new schedule model will use be able the new schedule module for instruction latencies in the if-converter (the logic is such that if there is no itineary we will use the new sched model for the latencies). Before, we queried "TTI->getInstructionLatency()" for the instruction latency and the extra prediction cost. Now, we query the TargetSchedule abstraction for the instruction latency and TargetInstrInfo for the extra predictation cost. The TargetSchedule abstraction will internally call "TTI->getInstructionLatency" if an itinerary exists, otherwise it will use the new schedule model. ATTENTION: Out of tree targets! (I will also send out an email later to LLVMDev) This means, if your target implements unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr *MI, unsigned *PredCost); and returns a value for "PredCost", you now also need to implement unsigned getPredictationCost(const MachineInstr *MI); (if your target uses the IfConversion.cpp pass) radar://15077010 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191671 91177308-0d34-0410-b5e6-96231b3b80d8		2013-09-30 15:28:56 +00:00
..
CostTable.h
Mangler.h
Target.td	Add an instruction deprecation feature to TableGen.	2013-09-12 10:28:05 +00:00
TargetCallingConv.h
TargetCallingConv.td	Add an OtherPreserved field to the CalleeSaved TableGen class.	2013-08-23 02:25:47 +00:00
TargetFrameLowering.h
TargetInstrInfo.h	IfConverter: Use TargetSchedule for instruction latencies	2013-09-30 15:28:56 +00:00
TargetIntrinsicInfo.h
TargetItinerary.td
TargetJITInfo.h
TargetLibraryInfo.h	[SystemZ] Use SRST to optimize memchr	2013-08-20 09:38:48 +00:00
TargetLowering.h	SelectionDAG: Use correct pointer size when lowering function arguments v2	2013-08-26 15:05:36 +00:00
TargetLoweringObjectFile.h
TargetMachine.h
TargetOpcodes.h
TargetOptions.h
TargetRegisterInfo.h	PrintVRegOrUnit	2013-08-23 17:48:53 +00:00
TargetSchedule.td	Even more spelling fixes for "instruction".	2013-09-28 13:42:22 +00:00
TargetSelectionDAG.td	Inplement aarch64 neon instructions in AdvSIMD(shift). About 24 shift instructions:	2013-09-04 09:28:24 +00:00
TargetSelectionDAGInfo.h	[SystemZ] Use SRST to optimize memchr	2013-08-20 09:38:48 +00:00
TargetSubtargetInfo.h	Added temp flag -misched-bench for staging in default changes.	2013-09-26 05:53:35 +00:00