llvm-6502/lib/CodeGen/SelectionDAG
Nadav Rotem 5a4552ca42 Fix #9190
The bug happens when the DAGCombiner attempts to optimize one of the patterns
of the SUB opcode. It tries to create a zero of type v2i64. This type is legal
on 32bit machines, but the initializer of this vector (i64) is target dependent.
Currently, the initializer attempts to create an i64 zero constant, which fails.
Added a flag to tell the DAGCombiner to create a legal zero, if we require that
the pass would generate legal types.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125391 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-11 19:20:37 +00:00
..
CMakeLists.txt
DAGCombiner.cpp Fix #9190 2011-02-11 19:20:37 +00:00
FastISel.cpp
FunctionLoweringInfo.cpp
InstrEmitter.cpp
InstrEmitter.h
LegalizeDAG.cpp
LegalizeFloatTypes.cpp
LegalizeIntegerTypes.cpp
LegalizeTypes.cpp
LegalizeTypes.h
LegalizeTypesGeneric.cpp
LegalizeVectorOps.cpp
LegalizeVectorTypes.cpp
Makefile
ScheduleDAGFast.cpp
ScheduleDAGList.cpp
ScheduleDAGRRList.cpp Introducing a new method of tracking register pressure. We can't 2011-02-04 03:18:17 +00:00
ScheduleDAGSDNodes.cpp Introducing a new method of tracking register pressure. We can't 2011-02-04 03:18:17 +00:00
ScheduleDAGSDNodes.h Introducing a new method of tracking register pressure. We can't 2011-02-04 03:18:17 +00:00
SDNodeDbgValue.h
SDNodeOrdering.h
SelectionDAG.cpp Remove comment about an argument that was removed couple of years ago. 2011-02-07 21:58:52 +00:00
SelectionDAGBuilder.cpp
SelectionDAGBuilder.h
SelectionDAGISel.cpp
SelectionDAGPrinter.cpp
TargetLowering.cpp
TargetSelectionDAGInfo.cpp