llvm-6502/lib/CodeGen
2010-05-25 21:49:43 +00:00
..
AsmPrinter Move the verbose asm output up a bit so it can be used in the special cases 2010-05-25 21:49:43 +00:00
PBQP
SelectionDAG Fix another variant of PR 7191. Also add a testcase 2010-05-25 18:47:23 +00:00
AggressiveAntiDepBreaker.cpp
AggressiveAntiDepBreaker.h
Analysis.cpp
AntiDepBreaker.h
BranchFolding.cpp Fix a bug which prevented tail merging of return instructions in 2010-05-03 14:35:47 +00:00
BranchFolding.h
CalcSpillWeights.cpp
CMakeLists.txt
CodePlacementOpt.cpp
CriticalAntiDepBreaker.cpp Remove trailing whitespace 2010-05-14 21:20:46 +00:00
CriticalAntiDepBreaker.h
DeadMachineInstructionElim.cpp
DwarfEHPrepare.cpp Code that needs a TargetMachine should have access to one directly, rather 2010-04-19 19:05:59 +00:00
ELF.h
ELFCodeEmitter.cpp
ELFCodeEmitter.h
ELFWriter.cpp
ELFWriter.h
ExactHazardRecognizer.cpp
ExactHazardRecognizer.h
GCMetadata.cpp
GCMetadataPrinter.cpp
GCStrategy.cpp
IfConversion.cpp
IntrinsicLowering.cpp Fixes for Microsoft Visual Studio 2010, from Steven Watanabe! 2010-05-11 06:17:44 +00:00
LatencyPriorityQueue.cpp
LiveInterval.cpp
LiveIntervalAnalysis.cpp - Change MachineInstr::findRegisterDefOperandIdx so it can also look for defs 2010-05-21 20:53:24 +00:00
LiveStackAnalysis.cpp
LiveVariables.cpp
LLVMTargetMachine.cpp MC: Add an MCLoggingStreamer, for use in debugging integrated-as mismatches. 2010-05-23 17:44:06 +00:00
LowerSubregs.cpp Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it 2010-05-06 20:33:48 +00:00
MachineBasicBlock.cpp
MachineCSE.cpp Make this LookAheadLimit, not the uninitialized LookAheadLeft. 2010-05-21 23:40:03 +00:00
MachineDominators.cpp Explicit template instantiations must happen in the template's immediately 2009-12-16 00:13:24 +00:00
MachineFunction.cpp Avoid adding duplicate function live-in's. 2010-05-24 21:33:37 +00:00
MachineFunctionAnalysis.cpp
MachineFunctionPass.cpp
MachineFunctionPrinterPass.cpp
MachineInstr.cpp Print symbolic SubRegIndex names on machine operands. 2010-05-25 19:49:38 +00:00
MachineLICM.cpp Teach MachineLICM and MachineSink how to clear kill flags conservatively 2010-05-13 20:34:42 +00:00
MachineLoopInfo.cpp
MachineModuleInfo.cpp
MachineModuleInfoImpls.cpp
MachinePassRegistry.cpp
MachineRegisterInfo.cpp Avoid adding duplicate function live-in's. 2010-05-24 21:33:37 +00:00
MachineSink.cpp Teach MachineLICM and MachineSink how to clear kill flags conservatively 2010-05-13 20:34:42 +00:00
MachineSSAUpdater.cpp Fix PR7096. When a block containing multiple defs is tail duplicated, the 2010-05-10 17:14:26 +00:00
MachineVerifier.cpp Teach the machine code verifier to use getSubRegisterRegClass(). 2010-05-18 17:31:12 +00:00
Makefile
ObjectCodeEmitter.cpp
OcamlGC.cpp
OptimizeExts.cpp
OptimizePHIs.cpp
Passes.cpp
PHIElimination.cpp Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it 2010-05-06 20:33:48 +00:00
PHIElimination.h Move REG_SEQUENCE removal to 2addr pass. 2010-05-05 18:45:40 +00:00
PostRASchedulerList.cpp - Change MachineInstr::findRegisterDefOperandIdx so it can also look for defs 2010-05-21 20:53:24 +00:00
PreAllocSplitting.cpp - Change MachineInstr::findRegisterDefOperandIdx so it can also look for defs 2010-05-21 20:53:24 +00:00
ProcessImplicitDefs.cpp It's not safe eliminate copies where src and dst have different sub-register indices. 2010-05-11 00:20:03 +00:00
PrologEpilogInserter.cpp Implement @llvm.returnaddress. rdar://8015977. 2010-05-22 01:47:14 +00:00
PrologEpilogInserter.h
PseudoSourceValue.cpp Fix memcheck-found leaks: one false positive from using new[], and one true 2010-03-04 22:15:01 +00:00
README.txt
RegAllocFast.cpp Add support for partial redefs to the fast register allocator. 2010-05-19 21:36:05 +00:00
RegAllocLinearScan.cpp improve portability to systems that don't have powf/modf (e.g. solaris 9) 2010-05-15 17:10:24 +00:00
RegAllocLocal.cpp Remember to update VirtRegLastUse when spilling without killing before a call. 2010-05-18 22:20:09 +00:00
RegAllocPBQP.cpp improve portability to systems that don't have powf/modf (e.g. solaris 9) 2010-05-15 17:10:24 +00:00
RegisterCoalescer.cpp
RegisterScavenging.cpp Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot. 2010-05-06 19:06:44 +00:00
ScheduleDAG.cpp Remove unused member variable. 2010-05-17 09:47:55 +00:00
ScheduleDAGEmit.cpp Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it 2010-05-06 20:33:48 +00:00
ScheduleDAGInstrs.cpp Fix the post-RA instruction scheduler to handle instructions referenced by 2010-05-19 22:57:06 +00:00
ScheduleDAGInstrs.h I got tired of VISIBILITY_HIDDEN colliding with the gcc enum. Rename it 2010-05-11 20:16:09 +00:00
ScheduleDAGPrinter.cpp
ShadowStackGC.cpp
ShrinkWrapping.cpp
SimpleHazardRecognizer.h
SimpleRegisterCoalescing.cpp Disable invalid coalescer assertion. 2010-05-25 00:15:18 +00:00
SimpleRegisterCoalescing.h
SjLjEHPrepare.cpp
SlotIndexes.cpp
Spiller.cpp Fixes for Microsoft Visual Studio 2010, from Steven Watanabe! 2010-05-11 06:17:44 +00:00
Spiller.h
StackProtector.cpp
StackSlotColoring.cpp Okay, bear with me here... 2010-05-25 21:44:26 +00:00
StrongPHIElimination.cpp Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it 2010-05-06 20:33:48 +00:00
TailDuplication.cpp Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it 2010-05-06 20:33:48 +00:00
TargetInstrInfoImpl.cpp
TargetLoweringObjectFileImpl.cpp Add support for initialized global data for darwin tls. Update comments 2010-05-25 21:28:50 +00:00
TwoAddressInstructionPass.cpp - Change MachineInstr::findRegisterDefOperandIdx so it can also look for defs 2010-05-21 20:53:24 +00:00
UnreachableBlockElim.cpp
VirtRegMap.cpp
VirtRegMap.h
VirtRegRewriter.cpp Teach VirtRegRewriter to handle spilling in instructions that have multiple 2010-05-21 16:36:13 +00:00
VirtRegRewriter.h

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelyhood the store may become dead.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvments:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4

//===---------------------------------------------------------------------===//

The scheduler should be able to sort nearby instructions by their address. For
example, in an expanded memset sequence it's not uncommon to see code like this:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

Each of the stores is independent, and the scheduler is currently making an
arbitrary decision about the order.

//===---------------------------------------------------------------------===//

Another opportunitiy in this code is that the $0 could be moved to a register:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

This would save substantial code size, especially for longer sequences like
this. It would be easy to have a rule telling isel to avoid matching MOV32mi
if the immediate has more than some fixed number of uses. It's more involved
to teach the register allocator how to do late folding to recover from
excessive register pressure.