llvm-6502/lib/CodeGen
Evan Cheng 5d088fee7c Fix a bug in spill weight computation. If the alias is a super-register, and the super-register is in the register class we are trying to allocate. Then add the weight to all sub-registers of the super-register even if they are not aliases.
e.g. allocating for GR32, bh is not used, updating bl spill weight.                                                                                                        
     bl should get the same spill weight otherwise it will be choosen                                                                                              
     as a spill candidate since spilling bh doesn't make ebx available.
This fix PR2866.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67574 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-23 22:57:19 +00:00
..
AsmPrinter Fix internal representation of fp80 to be the 2009-03-23 21:16:53 +00:00
SelectionDAG When unfolding a load during scheduling, the new operator node has 2009-03-23 20:20:43 +00:00
BranchFolding.cpp Turns out AnalyzeBranch can modify the mbb being analyzed. This is a nasty 2009-02-09 07:14:22 +00:00
CMakeLists.txt update 2009-03-11 22:52:25 +00:00
DeadMachineInstructionElim.cpp
ELFWriter.cpp Introduce new linkage types linkonce_odr, weak_odr, common_odr 2009-03-07 15:45:40 +00:00
ELFWriter.h
GCMetadata.cpp Eliminate several more unnecessary intptr_t casts. 2009-02-18 05:09:16 +00:00
GCMetadataPrinter.cpp
GCStrategy.cpp Eliminate several more unnecessary intptr_t casts. 2009-02-18 05:09:16 +00:00
IfConversion.cpp
IntrinsicLowering.cpp Introduce new linkage types linkonce_odr, weak_odr, common_odr 2009-03-07 15:45:40 +00:00
LatencyPriorityQueue.cpp
LiveInterval.cpp Two coalescer fixes in one. 2009-03-11 00:03:21 +00:00
LiveIntervalAnalysis.cpp Fix PR3391 and PR3864. Reg allocator infinite looping. 2009-03-23 18:24:37 +00:00
LiveStackAnalysis.cpp
LiveVariables.cpp Fix PR3243: a LiveVariables bug. When HandlePhysRegKill is checking whether the last reference is also the last def (i.e. dead def), it should also check if last reference is the current machine instruction being processed. This can happen when it is processing a physical register use and setting the current machine instruction as sub-register's last ref. 2009-01-20 21:25:12 +00:00
LLVMTargetMachine.cpp Re-enable machine sinking pass now that the coalescer bugs and the AnalyzeBrnach bug are fixed. 2009-02-09 08:45:39 +00:00
LoopAligner.cpp
LowerSubregs.cpp Do not fold away subreg_to_reg if the source register has a sub-register index. That means the source register is taking a sub-register of a larger register. e.g. On x86 2009-03-23 07:19:58 +00:00
MachineBasicBlock.cpp
MachineDominators.cpp Eliminate several more unnecessary intptr_t casts. 2009-02-18 05:09:16 +00:00
MachineFunction.cpp Now that errs() is properly non-buffered, there's no need to 2009-03-23 15:57:19 +00:00
MachineInstr.cpp Model inline asm constraint which ties an input to an output register as machine operand TIED_TO constraint. This eliminated the need to pre-allocate registers for these. This also allows register allocator can eliminate the unneeded copies. 2009-03-23 08:01:15 +00:00
MachineLICM.cpp MachineLICM CSE should match destination register classes; avoid hoisting implicit_def's. 2009-02-27 00:02:22 +00:00
MachineLoopInfo.cpp
MachineModuleInfo.cpp Remove dead code. 2009-02-03 19:46:28 +00:00
MachinePassRegistry.cpp
MachineRegisterInfo.cpp
MachineSink.cpp Fix PR3522. It's not safe to sink into landing pad BB's. 2009-02-15 08:36:12 +00:00
MachOWriter.cpp It makes no sense to have a ODR version of common 2009-03-11 20:14:15 +00:00
MachOWriter.h Rename getABITypeSize to getTypePaddedSize, as 2009-01-12 20:38:59 +00:00
Makefile
OcamlGC.cpp Registry.h should not depend on CommandLine.h. 2009-01-16 07:02:28 +00:00
Passes.cpp
PBQP.cpp
PBQP.h
PHIElimination.cpp Reapply r67049, with the test adjusted for darwin 2009-03-17 09:46:22 +00:00
PhysRegTracker.h
PostRASchedulerList.cpp Add parentheses to pacify gcc-4.3. 2009-03-11 09:04:34 +00:00
PreAllocSplitting.cpp Give the pre-alloc splitter access to the VirtRegMap. It doesn't do anything 2009-03-14 21:40:05 +00:00
PrologEpilogInserter.cpp Apply the patch requested in PR3846. 2009-03-20 05:08:24 +00:00
PseudoSourceValue.cpp Now that errs() is properly non-buffered, there's no need to 2009-03-23 15:57:19 +00:00
README.txt
RegAllocBigBlock.cpp Adjust the sizes for a few SmallVectors to reflect their usage. 2009-02-12 17:29:01 +00:00
RegAllocLinearScan.cpp Fix a bug in spill weight computation. If the alias is a super-register, and the super-register is in the register class we are trying to allocate. Then add the weight to all sub-registers of the super-register even if they are not aliases. 2009-03-23 22:57:19 +00:00
RegAllocLocal.cpp Added MachineInstr::isRegTiedToDefOperand to check for two-addressness. 2009-03-19 20:30:06 +00:00
RegAllocPBQP.cpp r66870 missed this out. 2009-03-17 15:46:15 +00:00
RegAllocSimple.cpp
RegisterCoalescer.cpp
RegisterScavenging.cpp
ScheduleDAG.cpp When scheduling a block in parts, keep track of the overall 2009-02-11 04:27:20 +00:00
ScheduleDAGEmit.cpp When scheduling a block in parts, keep track of the overall 2009-02-11 04:27:20 +00:00
ScheduleDAGInstrs.cpp When scheduling a block in parts, keep track of the overall 2009-02-11 04:27:20 +00:00
ScheduleDAGInstrs.h When scheduling a block in parts, keep track of the overall 2009-02-11 04:27:20 +00:00
ScheduleDAGPrinter.cpp Apparently some MachineBasicBlock's don't have corresponding llvm basic blocks. 2009-02-11 23:42:39 +00:00
ShadowStackGC.cpp Introduce new linkage types linkonce_odr, weak_odr, common_odr 2009-03-07 15:45:40 +00:00
SimpleRegisterCoalescing.cpp My last coalescer fix introduced a subtler one. It's aborting a commuting optimization too late and left the live intervals to be out of sync with instructions. This fixes 8b10b. 2009-03-11 22:18:44 +00:00
SimpleRegisterCoalescing.h ReMaterializeTrivialDef need to trim the live interval to the last kill if the copy kills the source register. This fixes uint64tof64.ll after ARM::MOVi is marked as isAsCheapAsAMove. 2009-02-05 08:45:04 +00:00
Spiller.cpp Fixed build warnings for unused variables. 2009-03-20 13:49:20 +00:00
Spiller.h Spiller may unfold load / mod / store instructions as an optimization when the would be loaded value is available in a register. It needs to check if it's legal to clobber the register. Also, the register can contain values of multiple spill slots, make sure to check all instead of just the one being unfolded. 2009-03-17 01:23:09 +00:00
StackProtector.cpp When we split a basic block, there's a default branch to the newly created BB. 2009-03-06 01:41:15 +00:00
StackSlotColoring.cpp Enable stack slot coloring DCE. Evan's spiller fixes were needed before this could happen. 2009-02-26 04:47:57 +00:00
StrongPHIElimination.cpp
TargetInstrInfoImpl.cpp Explicitly pass in debug location information to BuildMI. 2009-02-03 02:29:34 +00:00
TwoAddressInstructionPass.cpp Model inline asm constraint which ties an input to an output register as machine operand TIED_TO constraint. This eliminated the need to pre-allocate registers for these. This also allows register allocator can eliminate the unneeded copies. 2009-03-23 08:01:15 +00:00
UnreachableBlockElim.cpp Rename getAnalysisToUpdate to getAnalysisIfAvailable. 2009-01-28 13:14:17 +00:00
VirtRegMap.cpp Add newlines at end of file (this can annoy gcov) 2009-03-14 01:53:05 +00:00
VirtRegMap.h Convert VirtRegMap to a MachineFunctionPass. 2009-03-13 05:55:11 +00:00

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelyhood the store may become dead.

//===---------------------------------------------------------------------===//

I think we should have a "hasSideEffects" flag (which is automatically set for
stuff that "isLoad" "isCall" etc), and the remat pass should eventually be able
to remat any instruction that has no side effects, if it can handle it and if
profitable.

For now, I'd suggest having the remat stuff work like this:

1. I need to spill/reload this thing.
2. Check to see if it has side effects.
3. Check to see if it is simple enough: e.g. it only has one register
destination and no register input.
4. If so, clone the instruction, do the xform, etc.

Advantages of this are:

1. the .td file describes the behavior of the instructions, not the way the
   algorithm should work.
2. as remat gets smarter in the future, we shouldn't have to be changing the .td
   files.
3. it is easier to explain what the flag means in the .td file, because you
   don't have to pull in the explanation of how the current remat algo works.

Some potential added complexities:

1. Some instructions have to be glued to it's predecessor or successor. All of
   the PC relative instructions and condition code setting instruction. We could
   mark them as hasSideEffects, but that's not quite right. PC relative loads
   from constantpools can be remat'ed, for example. But it requires more than
   just cloning the instruction. Some instructions can be remat'ed but it
   expands to more than one instruction. But allocator will have to make a
   decision.

4. As stated in 3, not as simple as cloning in some cases. The target will have
   to decide how to remat it. For example, an ARM 2-piece constant generation
   instruction is remat'ed as a load from constantpool.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvments:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4