llvm-6502/test/CodeGen
Chris Lattner 5eecb7f164 This adds in some code (currently disabled unless you pass
-enable-smarter-addr-folding to llc) that gives CGP a better
cost model for when to sink computations into addressing modes.
The basic observation is that sinking increases register 
pressure when part of the addr computation has to be available
for other reasons, such as having a use that is a non-memory
operation.  In cases where it works, it can substantially reduce
register pressure.

This code is currently an overall win on 403.gcc and 255.vortex
(the two things I've been looking at), but there are several 
things I want to do before enabling it by default:

1. This isn't doing any caching of results, so it is much slower 
   than it could be.  It currently slows down release-asserts llc 
   by 1.7% on 176.gcc: 27.12s -> 27.60s.
2. This doesn't think about inline asm memory operands yet.
3. The cost model botches the case when the needed value is live
   across the computation for other reasons.

I'll continue poking at this, and eventually turn it on as llcbeta.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60074 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-26 02:00:14 +00:00
..
Alpha Correct some thinkos in the expansion of ADD/SUB 2008-11-12 08:23:26 +00:00
ARM - Register scavenger should use MachineRegisterInfo and internal map to find the first use of a register after a given machine instruction. 2008-11-20 02:32:35 +00:00
CBackend
CellSPU CellSPU: 2008-11-25 17:29:43 +00:00
CPP
Generic Test add-with-overflow with fast ISel. 2008-11-24 05:23:38 +00:00
IA64
Mips Fix PR2667: add soft float support for sint_to_fp/uint_to_fp 2008-11-10 17:36:26 +00:00
PowerPC Remove these, which test for optimizations that 2008-11-17 18:57:45 +00:00
SPARC
X86 This adds in some code (currently disabled unless you pass 2008-11-26 02:00:14 +00:00
XCore Reapply r59464, this time using the correct type 2008-11-18 09:15:03 +00:00