Jakob Stoklund Olesen 5f2316a3b5 Switch AllocationOrder to using RegisterClassInfo instead of a BitVector ... of reserved registers. Use RegisterClassInfo in RABasic as well. This slightly changes som allocation orders because RegisterClassInfo puts CSR aliases last. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132581 91177308-0d34-0410-b5e6-96231b3b80d8		2011-06-03 20:34:53 +00:00
..
Analysis	When merging MustAlias and PartialAlias, chose PartialAlias instead	2011-06-03 20:17:36 +00:00
Archive
Assembler
Bindings/Ocaml
Bitcode	Add missing newlines.	2011-05-28 01:35:58 +00:00
BugPoint
CodeGen	Switch AllocationOrder to using RegisterClassInfo instead of a BitVector	2011-06-03 20:34:53 +00:00
DebugInfo	Fix a regression I recently introduced by removing DwarfRegNum of	2011-05-27 22:15:01 +00:00
ExecutionEngine	Reverted r132135 per Xerxes request. These tests are passing for his setup. Requires more research.	2011-05-31 21:50:33 +00:00
Feature
FrontendAda
FrontendC	This should have been a C++ testcase.	2011-06-02 22:26:15 +00:00
FrontendC++	Accomodate front-ends which use private instead of internal here.	2011-06-03 19:21:05 +00:00
FrontendFortran
FrontendObjC
FrontendObjC++
Integer
lib
Linker
LLVMC
MC	Fix ssat and ssat16 encodings for ARM and Thumb. The bit position value	2011-05-31 03:33:27 +00:00
Object
Other
Scripts
TableGen
Transforms	Bail on unswitching a switch statement for a case with a critical edge. We name	2011-06-03 06:27:15 +00:00
Unit
Verifier
CMakeLists.txt
lit.cfg
lit.site.cfg.in
Makefile
Makefile.tests
site.exp.in
TestRunner.sh