llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-14 16:33:28 +00:00

History

Benjamin Kramer 914f8c4825 When the legalizer is splitting vector shifts, the result may not have the right shift amount type.

Fix that by adding a cast to the shift expander. This came up with vector shifts
on sse-less X86 CPUs.

   <2 x i64>       = shl <2 x i64> <2 x i64>
-> i64,i64         = shl i64 i64; shl i64 i64
-> i32,i32,i32,i32 = shl_parts i32 i32 i64; shl_parts i32 i32 i64

Now we cast the last two i64s to the right type. Fixes the crash in PR14668.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173615 91177308-0d34-0410-b5e6-96231b3b80d8

2013-01-27 11:19:11 +00:00

ARM

Fixed the condition codes for the atomic64 min/umin code generation on ARM. If the sutraction of the higher 32 bit parts gives a 0 result, we need to do the store operation.

2013-01-25 10:39:49 +00:00

CPP

…

Generic

For inline asm:

2013-01-11 18:12:39 +00:00

Hexagon

Add indexed load/store instructions for offset validation check.

2013-01-17 18:42:37 +00:00