Tim Northover 659e09e372 DAGLegalize: add last-ditch type-legalization for VSELECT. ... When LLVM sees something like (v1iN (vselect v1i1, v1iN, v1iN)) it can decide that the result is OK (v1i64 is legal on AArch64, for example) but it still need scalarising because of that v1i1. There was no code to do this though. AArch64 and ARM64 have DAG combines to produce efficient code and prevent that occuring in *most* such situations, but there are edge cases that they miss. This adds a legalization to cope with that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205626 91177308-0d34-0410-b5e6-96231b3b80d8		2014-04-04 14:49:30 +00:00
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AArch64
ARM	ARM: yet another round of ARM test clean ups	2014-04-03 23:47:24 +00:00
ARM64	DAGLegalize: add last-ditch type-legalization for VSELECT.	2014-04-04 14:49:30 +00:00
CPP
Generic
Hexagon
Inputs
Mips	[mips] Add more Octeon cnMips instructions	2014-04-02 18:40:43 +00:00
MSP430	Mark FPB as a reserved register when needed.	2014-04-02 13:13:56 +00:00
NVPTX	Optimize away unnecessary address casts.	2014-04-03 21:18:25 +00:00
PowerPC	[PowerPC] Add some missing VSX bitcast patterns	2014-04-01 19:24:27 +00:00
R600	R600: Correct opcode for BFE_INT	2014-04-03 20:19:29 +00:00
SPARC
SystemZ
Thumb	ARM: yet another round of ARM test clean ups	2014-04-03 23:47:24 +00:00
Thumb2	ARM: fix test case missed in previous roundup	2014-04-04 01:19:56 +00:00
X86	[RegAllocGreedy][Last Chance Recoloring] Emit diagnostics when last chance	2014-04-04 02:05:21 +00:00
XCore